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AD6140 数据表(PDF) 7 Page - Analog Devices |
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AD6140 数据表(HTML) 7 Page - Analog Devices |
7 / 8 page REV. 0 AD6140 –7– otherwise, the expected gain will not be obtained from the AD6140. In addition to the mixer, there is a mixer post- amplifier within the AD6140. The total gain from the mixer and mixer post-amplifier is 5 dB. The Σ∆ modulator uses a 6.144 MHz clock, which is a differen- tial ECL input. There is an ECL-to-CMOS converter on the AD6140, which converts this differential ECL input into a single-ended CMOS signal. This 6.144 MHz single-ended CMOS clock is provided at Pin 7 ( Σ∆_CLOCK_OUT). The output data of the AD6140 is a 6.144 MHz single bitstream at Pin 6 ( Σ∆_DATA_OUT). The signal gain through the Σ∆ modulator is –0.77 dB. Within the Σ∆ modulator, the data output digital bitstream is fed through a 1-bit D/A converter and is fed back to numerous internal points. The level of this feedback signal, known as the full-scale level, defines the Σ∆ modulator input signal level, which would result in the output digital bitstream containing the maximum number of ones possible. This condition, known as maximum ones density, represents the maximum in-band out- put signal power of the Σ∆ modulator. The full-scale level is set to 2 V p-p or –4.77 dBm (relative to 1500 Ω). However, if a signal into the modulator is –4.77 dBm, the modulator will enter an unstable state. Consequently, the maximum input to the modulator is constrained to 5 dB less than the signal, which would produce maximum ones density. This level, defined as the clip level, is –9.77 dBm (relative to 1500 Ω). The maximum signal into the modulator does not correspond to maximum ones density. The entire dynamic range of the result- ing analog to digital converter ( Σ∆ modulator plus decimation filter) is not realized. In order to relate the maximum signal into the modulator to the maximum signal out of the modulator, a gain of 5 dB should be applied in the decimation filter. As can be seen in Figure 5, the output signal to noise ratio will increase until a point at which it rapidly degrades. This point represents the input signal level where the Σ∆ modulator has become unstable. As a result, the maximum input signal level is constrained by the point at which it is so high that instability occurs in the modulator. Dynamic range is defined as the differ- ence between the integrated noise floor (within a particular bandwidth) and the power in the output signal just before the Σ∆ modulator has become unstable. For a typical 6.25 kHz bandwidth centered around 192 kHz, the AD6140 has 83 dB of dynamic range. In order to increase the range of useful input signals of the AD6140, an AGC detector is employed which senses the input signal level to the Σ∆ modulator and adjusts the gain in the pream- plifier. The AGC circuitry provides 13 dB of automatic gain control range. The AGC operates when the internal AGC voltage is between 700 mV (minimum gain) and 1.55 V (maximum gain). This voltage can be measured on the AGC_CAPACITOR pin (Pin 13). The AD6140 can be configured with the chip powered up or down. In order to power the chip down, set pin POWER_DOWN (Pin 9) high. In order to power it up, set pin POWER_DOWN (Pin 9) low. Finally, an auxiliary amplifier used for biasing an external dis- crete LNA is provided with the AD6140. FREQUENCY PLAN The AD6140 and its Σ∆ modulator are designed for a specific frequency plan: a 6.144 MHz master clock, a 49.6 MHz first IF input, and a 192 kHz center frequency in the bandpass Σ∆ modulator. The local oscillator may use high-side or low-side injection. The specifications for the AD6140 are only valid for this frequency plan. Any deviation from this frequency plan may result in degradation of the specified performance. Furthermore, there are only specific frequency plans which will result in ac- ceptable performance for most applications. To avoid problems, do not change the frequency plan. USING THE AD6140 In this section, we will examine a few areas of special impor- tance and include a few general applications tips. As is true of any device operating in the IF frequency range, special care must be taken in PC board layout. The location of the particular grounding points must be considered, with the objective of minimizing any unwanted signal coupling. Specifically, care should be taken in the layout of the IF and LO signal paths as well as the data and clock digital bit-streams. Layout of these portions of the PC board require special attention in order to ensure that the high frequency portions of these signals do not couple into other signals in the system. In order to maintain balance in differential signal levels, be sure to keep short and equal length transmission lines. The power supplies should be decoupled to ensure a clean dc signal. Special care should be taken with respect to ensuring that the BUFFER_VDD is especially clean and at the appropriate levels since the output in-band noise floor is particularly sensi- tive to this supply. The IF input signal should be impedance matched and ac coupled. The impedance looking into the IF input pin is typi- cally a 2.5 k Ω resistance in parallel with a 12 pF capacitance. The 1 V reference signal should be regulated and filtered. The value of the BIAS_RESISTOR (Pin 16) is 39 k Ω. The bias resistor sets the current consumption of the AD6140. Because the AD6140 was characterized with a 39 k Ω bias resistor, this is the only value for which the AD6140 specifications are guaran- teed. Maximum current consumption is measured when the AD6140 is operating at maximum gain. The AGC integration capacitor should be large enough to by- pass any externally-generated noise on the internal AGC line to ground in addition to providing a path for the charging and discharging of the AGC current. In the Motorola ReFLEX chipset solution, this capacitor is 0.1 µF. The AGC time con- stant is switch-selectable with the AGC_TC_SELECT pin (Pin 10). The AGC time constant has a typical current ratio of 56:1 when in the fast mode relative to slow mode. The nominal AGC current in the fast (high current) position is 2.8 µA and in the slow (low current) position is 50 nA. The AGC time constant may be calculated from Equation 1. T CV I = (1) where T is the AGC time constant in seconds, C is the value of the AGC capacitor in Farads, V is the full-scale change in the AGC voltage, and I is the charging current in amperes. OBSOLETE |
类似零件编号 - AD6140_15 |
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类似说明 - AD6140_15 |
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