TEA1755T

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© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 1 — 25 October 2012

9 of 35

NXP Semiconductors

TEA1755T

HV start-up DCM/QR flyback and DCM/QR PFC controllers

Operating near the PFC OVP level causes the PFC stage on-time to decrease rapidly to

zero.

To reduce the response time, in case of load variation, the PFCCOMP pin is clamped to a

minimum level of 2 V during PFC operation. Clamping prevents the on-time increasing too

much and improves the PFC response time when the load decreases again.

7.2.2 Valley switching and demagnetization (PFCAUX pin)

The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry

connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the

voltage across the PFC MOSFET. To reduce switching losses and ElectroMagnetic

Interference (EMI), the next stroke is started when the voltage across the PFC MOSFET

is at its minimum (valley switching).

If a demagnetization signal is not detected on the PFCAUX pin, the controller generates a

Zero-Current Signal (ZCS) 48

s after the last PFC MOSFET gate signal.

If valley signal is not detected on the PFCAUX pin, the controller generates a valley signal

4.2

s after demagnetization is detected.

To protect the internal circuitry during, for example, lightning events, add a 5 k

 series

resistor to the PFCAUX pin. To prevent incorrect switching due to external interference,

place the resistor close to the IC on the PCB.

7.2.3 Frequency limitation

To optimize the transformer and minimize switching losses, the switching frequency is

limit, the system switches to DCM. The PFC MOSFET is only switched on at a minimum

voltage across the switch (valley switching).

7.2.4 Mains voltage compensation (VINSENSE pin)

The equation for the transfer function of a power factor corrector contains the square of

the mains input voltage. In a typical application, this results in a low bandwidth for low

mains input voltages. At high mains input voltages, the Mains Harmonic Reduction (MHR)

requirements are hard to meet.

To compensate for the influence of the mains input voltage, the TEA1755T contains a

correction circuit. The average input voltage is measured using the VINSENSE pin and

the information is fed to an internal compensation circuit. Using this compensation, it is

possible to keep the regulation loop bandwidth constant over the mains input range. This

feature gives a fast transient response on load steps while still complying with class-D

MHR requirements.

In a typical application, a resistor and two capacitors connected to the PFCCOMP pin set

the regulation loop bandwidth.

7.2.5 Soft-start (PFCSENSE pin)

To prevent audible transformer noise at start-up or during hiccup, the soft-start function

charges the capacitor to: