©

1996

DATA SHEET

HETERO JUNCTION FIELD EFFECT TRANSISTOR

NE32500, NE27200

C to Ka BAND SUPER LOW NOISE AMPLIFIER

N-CHANNEL HJ-FET CHIP

DESCRIPTION

NE32500 and NE27200 are Hetero Junction FET chip that utilizes the hetero junction between Si-doped AlGaAs

and undoped InGaAs to create high mobility electrons. Its excellent low noise and high associated gain make it suitable

for commercial systems, industrial and space applications.

FEATURES

•

Super Low Noise Figure & High Associated Gain

•

µm

•

µm

ORDERING INFORMATION

PART NUMBER

QUALITY GRADE

NE32500

Standard (Grade D)

NE27200

Special, specific (Grade C and B)

Drain to Source Voltage

4.0

V

Gate to Source Voltage

–3.0

V

Drain Current

mA

Total Power Dissipation

200

mW

Channel Temperature

175

°C

Storage Temperature

–65 to +175

°C

* Chip mounted on a Alumina heatsink (size: 3

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

TEST CONDITIONS

Gate to Source Leak Current

–

0.5

10

Saturated Drain Current

20

60

90

mA

Gate to Source Cutoff Voltage

–0.2

–0.7

–2.0

V

µA

Transconductance

45

60

–

mS

Thermal Resistance

–

–

260

˚C/W

channel to case

Noise Figure

NF

–

0.45

0.55

dB

Associated Gain

11.0

12.5

–

dB

RF performance is determined by packaging and testing 10 chips per wafer.

Wafer rejection criteria for standard devices is 2 rejects per 10 samples.

Document No. P11512EJ2V0DS00 (2nd edition)

Date Published January 1997 N

Printed in Japan