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MC-4R64CEE6C-745 数据表(PDF) 6 Page - NEC |
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MC-4R64CEE6C-745 数据表(HTML) 6 Page - NEC |
6 / 16 page Preliminary Data Sheet M14537EJ1V1DS00 6 MC-4R64CEE6B, 4R64CEE6C (2/2) Signal I/O Type Description RSCK I VCMOS Serial clock input. Clock source used to read from and write to the RDRAM control registers. SA0 I SVDD Serial Presence Detect Address 0. SA1 I SVDD Serial Presence Detect Address 1. SA2 I SVDD Serial Presence Detect Address 2. SCL I SVDD Serial Presence Detect Clock. SDA I/O SVDD Serial Presence Detect Data (Open Collector I/O). SIN I/O VCMOS Serial I/O for reading from and writing to the control registers. Attaches to SIO0 of the first RDRAM on the module. SOUT I/O VCMOS Serial I/O for reading from and writing to the control registers. Attaches to SIO1 of the last RDRAM on the module. SVDD — — SPD Voltage. Used for signals SCL, SDA, SWP, SA0, SA1 and SA2. SWP I SVDD Serial Presence Detect Write Protect (active high). When low, the SPD can be written as well as read. VCMOS — — CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT. VDD — — Supply voltage for the RDRAM core and interface logic. VREF — — Logic threshold reference voltage for RSL signals. |
类似零件编号 - MC-4R64CEE6C-745 |
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类似说明 - MC-4R64CEE6C-745 |
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