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MC-45D32CC721KFA-C80 数据表(PDF) 1 Page - NEC

部件名 MC-45D32CC721KFA-C80
功能描述  32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE
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制造商  NEC [NEC]
网页  http://www.nec.com/
标志 NEC - NEC

MC-45D32CC721KFA-C80 数据表(HTML) 1 Page - NEC

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The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
©
2000
MOS INTEGRATED CIRCUIT
MC-45D32CC721
Document No. M14900EJ1V0DS00 (1st edition)
Date Published June 2000 NS CP(K)
Printed in Japan
PRELIMINARY DATA SHEET
32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-45D32CC721 is a 33,554,432 words by 72 bits DDR synchronous dynamic RAM module on which 18
pieces of 128M DDR SDRAM:
µPD45D128842 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 33,554,432 words by 72 bits organization (ECC type)
• Clock frequency
Part number
/CAS latency
Clock frequency
Module type
(MAX.)
MC-45D32CC721KFA-C75
CL = 2.5
133 MHz
DDR SDRAM
CL = 2
100 MHz
Unbuffered DIMM
MC-45D32CC721KFA-C80
CL = 2.5
125 MHz
Design specification
CL = 2
100 MHz
Rev.0.9 compliant
• Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge
• Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
• Quad internal banks operation
• Possible to assert random column address in every clock cycle
• Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• 2.5 V ± 0.2 V Power supply for VDD
• 2.5 V ± 0.2 V Power supply for VDDQ
• SSTL_2 compatible with all signals
• 4,096 refresh cycles / 64 ms
• Burst termination by Precharge command and Burst stop command
• 184-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD


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