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ADC08L060 数据表(PDF) 7 Page - Texas Instruments |
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ADC08L060 数据表(HTML) 7 Page - Texas Instruments |
7 / 29 page ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 Converter Electrical Characteristics (continued) The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1)(2) (3) Typical Limits Units Symbol Parameter Conditions (4) (4) (Limits) AC ELECTRICAL CHARACTERISTICS fC1 Maximum Conversion Rate 80 60 MHz (min) fC2 Minimum Conversion Rate 10 MHz tCL Minimum Clock Low Time 0.62 ns (min) tCH Minimum Clock High Time 0.62 ns (min) 5 %(min) DC Clock Duty Cycle 95 %(max) tOH Output Hold Time CLK to Data Invalid 5.2 ns 5.0 ns (min) tOD Output Delay CLK to Data Transition 7.1 9.4 ns (max) Pipeline Delay (Latency) 5 Clock Cycles tAD Sampling (Aperture) Delay CLK Rise to Acquisition of Data 2.6 ns tAJ Aperture Jitter 2 ps rms Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the rise of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tAD after the clock goes high. APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input noise. CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one clock period. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. Measured at 60 MSPS with a ramp input. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 1½ LSB below VRT and is defined as: Vmax + 1.5 LSB – VRT (1) where Vmax is the voltage at which the transition to the maximum (full scale) code occurs. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. The end point test method is used. Measured at 60 MSPS with a ramp input. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. it is defined as the ratio of the power in the second and third order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dBFS. LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is (VRT − VRB) / 2 n (2) where “n” is the ADC resolution, which is 8 in the case of the ADC08L060. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADC08L060 |
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