ADCS7476, ADCS7477, ADCS7478

SNAS192F – APRIL 2003 – REVISED MARCH 2013

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PIN DESCRIPTIONS

Pin No.

Symbol

Description

ANALOG I/O

3

DIGITAL I/O

Digital clock input. The range of frequencies for this input is 10 kHz to 20 MHz, with ensured

4

SCLK

performance at 20 MHz. This clock directly controls the conversion and readout processes.

5

SDATA

Digital data output. The output words are clocked out of this pin by the SCLK pin.

6

CS

Chip select. A conversion process begins on the falling edge of CS.

POWER SUPPLY

Positive supply pin. These pins should be connected to a quiet +2.7V to +5.25V source and bypassed

1

to GND with 0.1 µF and 1 µF monolithic capacitors located within 1 cm of the power pin. The

ADCS7476/77/78 uses this power supply as a reference, so it should be thoroughly bypassed.

2

GND

The ground return for the supply.

Block Diagram

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2)

−0.3V to +6.5V

Voltage on Any Analog Pin to GND

Voltage on Any Digital Pin to GND

-0.3V to 6.5V

±10 mA

ESD Susceptibility

Human Body Model

3500V

Machine Model

200V

Soldering Temperature, Infrared,

10 seconds

215°C

Junction Temperature

+150°C

Storage Temperature

−65°C to +150°C

(1)

Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be

impaired. Functional operability under any of these conditions is not implied. Exposure to maximum ratings for extended periods may

affect device reliability.

(2)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3)

Except power supply pins.

2

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