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AM4961AGHTR-G1 数据表(PDF) 6 Page - Diodes Incorporated |
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AM4961AGHTR-G1 数据表(HTML) 6 Page - Diodes Incorporated |
6 / 17 page AM4961A Document number: DS36626 Rev. 1 - 2 6 of 17 www.diodes.com October 2013 © Diodes Incorporated AM4961A A Product Line of Diodes Incorporated Functional Descriptions H-Bias – Hall Bias Output This is a 1.25V nominal voltage source to bias a differential un-buffered Hall element sensor. If a Hall element requires a lower voltage than the H-Bias output, connect an appropriate value resistor between the H-Bias pin and the Hall element supply pin. H+ and H- – Hall Inputs The rotor position is detected by a Hall sensor, with the output applied to the H+ and H-pins. This sensor can be either a 4 pin 'naked' Hall device or of the 3 pin buffered switching type. For a 4 pin device the differential Hall output signal is connected to the H+ and H- pins. For a buffered Hall sensor the Hall device output is attached to the H+ pin, with a pull-up attached if needed, whilst the H- pin has an external potential divider attached to hold the pin at half Vref. When H+ is high in relation to H-, out2 is the active drive. VREF – Output Reference Voltage This is a 6V nominal reference output voltage. It is designed to 'source' current and therefore it will not 'sink' any current from a higher voltage. The total current drawn from the VREF pin by any external circuitry, such as the minimum speed potential divider to VMIN pin, should not exceed 5mA. COSC Pin A capacitor at the COSC pin generates a triangular waveform which is compared with VPWM (or VMIN) to generate output Pulse Width Modulated (PWM) drive for speed control. A capacitor of 100pf capacitor connected between COSC and ground a 25 kHz triangle wave with high level voltage is 0.3VCC typical and low level voltage of 0.16VCC typical. For 12V supply, the high and low level thresholds are 3.6V and 1.95V. VPWM - Speed control Input The voltage applied to the VPWM pin provides control of the motor speed by varying the PWM drive ratio at the out1 and out2 outputs. The control signal should be a variable DC voltage input of range 3.6V to 1.95V for nominal 12V supply, representing 0% to 100% drive respectively. If variable speed control is not required this pin can be tied to an external potential divider to set a fixed speed or tied to ground to provide full speed i.e. 100% PWM drive. If external input PWM signal is used to control the speed, this input PWM signal needs to be converted to a DC voltage to meet the VPWM pin input range. VMIN – Minimum Speed Setting A voltage can be set on this pin via a potential divider between the VREF (or Supply) and GND pins. This voltage is monitored by the VPWM pin to clamp the VPWM control voltage so that it does not rise above VMIN voltage. As a higher voltage on the VPWM pin represents a lower speed, the VMIN setting prevents the motor speed going lower than the minimum speed set by the VMIN pin. When the VMIN voltage is higher than the lowest speed setting voltage allowed (The lowest speed voltage is about 0.28VCC), the fan speed is maintained at the at the lowest speed. CT Pin – Locked Rotor Timing Capacitor The CT pin will have a capacitor connected to ground. It is a multi-function pin providing timing for the lock detect and auto-restart. Different rates of charge and discharge of CT capacitor depending on the mode of operation (fan operation status) give the lock-detect time (TLCKDET) and lock time (TOFF) before next auto-start retry. When the motor is running, the capacitor is discharged at every Hall signal change. CT pin provides the timing for the Locked Rotor monitor. In normal operation, Lock Detect is enabled. If the Hall signal does not change (i.e. a rotor lock condition) within the Lock Detect time (TLCKDET), the outputs are disabled. In this condition the motor will not be driven for a set time TOFF. This TOFF time depends on the external CT capacitor value and its internal discharge current (IDHG). After the TOFF period device enter auto-restart phase to re-start the motor with a new Lock Detect time. If the motor has not turned to generate a transition on the Hall inputs by the end this TLCKDET period, motor re-enters motor lock TOFF period with outputs disabled. If the Hall signal change is detected, the motor is deemed as running and goes into lock-detection mode. The TLCKDET and TOFF are determined by the value of the external capacitor on the CT pin and the internal charge and discharge currents during these time periods. The currents during, TLCKDET and TOFF are ICHG, and IDHG respectively. FG – Frequency Generator (Tachometer) Output This is the Frequency Generator output and is a buffered signal from the Hall sensor. This is an open collector drive giving an active pull down with the high level being provided by an external pull up resistor. |
类似零件编号 - AM4961AGHTR-G1 |
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类似说明 - AM4961AGHTR-G1 |
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