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ADF7021 数据表(PDF) 5 Page - Analog Devices

部件名 ADF7021
功能描述  High Performance Narrow-Band Transceiver IC
Download  64 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADF7021 数据表(HTML) 5 Page - Analog Devices

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Data Sheet
ADF7021
Rev. B | Page 5 of 64
SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C.
All measurements are performed with the EVAL-ADF7021DBx using the PN9 data sequence, unless otherwise noted.
RF AND PLL SPECIFICATIONS
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RF CHARACTERISTICS
See Table 9 for required VCO_BIAS and
VCO_ADJUST settings
Frequency Ranges (Direct Output)
160
650
MHz
External inductor VCO
862
950
MHz
Internal inductor VCO
Frequency Ranges (RF Divide-by-2 Mode)
80
325
MHz
External inductor VCO, RF divide-by-2 enabled
431
475
MHz
Internal inductor VCO, RF divide-by-2 enabled
Phase Frequency Detector (PFD) Frequency1
RF/256
26/30
MHz
Crystal reference/external reference
PHASE-LOCKED LOOP (PLL)
VCO Gain2
868 MHz, Internal Inductor VCO
58
MHz/V
VCO_ADJUST = 0, VCO_BIAS = 8
434 MHz, Internal Inductor VCO
29
MHz/V
VCO_ADJUST = 0, VCO_BIAS = 8
426 MHz, External Inductor VCO
27
MHz/V
VCO_ADJUST = 0, VCO_BIAS = 3
160 MHz, External Inductor VCO
6
MHz/V
VCO_ADJUST = 0, VCO_BIAS = 2
Phase Noise (In-Band)
868 MHz, Internal Inductor VCO
−97
dBc/Hz
10 kHz offset, PA = 10 dBm, VDD = 3.0 V,
PFD = 19.68 MHz, VCO_BIAS = 8
433 MHz, Internal Inductor VCO
−103
dBc/Hz
10 kHz offset, PA = 10 dBm, VDD = 3.0 V,
PFD = 19.68 MHz, VCO_BIAS = 8
426 MHz, External Inductor VCO
−95
dBc/Hz
10 kHz offset, PA = 10 dBm, VDD = 3.0 V,
PFD = 9.84 MHz, VCO_BIAS = 3
Phase Noise (Out-of-Band)
−124
dBc/Hz
1 MHz offset, fRF = 433 MHz, PA = 10 dBm,
VDD = 3.0 V, PFD = 19.68 MHz, VCO_BIAS = 8
Normalized In-Band Phase Noise Floor3
−203
dBc/Hz
PLL Settling
40
µs
Measured for a 10 MHz frequency step to within
5 ppm accuracy, PFD = 19.68 MHz, loop
bandwidth (LBW) = 100 kHz
REFERENCE INPUT
Crystal Reference4
3.625
26
MHz
External Oscillator4, 5
3.625
30
MHz
Crystal Start-Up Time6
XTAL Bias = 20 µA
0.930
ms
10 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V
XTAL Bias = 35 µA
0.438
ms
10 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V
Input Level for External Oscillator7
OSC1
0.8
V p-p
Clipped sine wave
OSC2
CMOS levels
V
ADC PARAMETERS
INL
±0.4
LSB
VDD = 2.3 V to 3.6 V, TA = 25°C
DNL
±0.4
LSB
VDD = 2.3 V to 3.6 V, TA = 25°C
1
The maximum usable PFD at a particular RF frequency is limited by the minimum N divide value.
2
VCO gain measured at a VCO tuning voltage of 1 V. The VCO gain varies across the tuning range of the VCO. The software package ADIsimPLL™ can be used to model this
variation.
3
This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance
as seen at the PA output: −203 + 10 log(fPFD) + 20 logN.
4
Guaranteed by design. Sample tested to ensure compliance.
5
A TCXO, VCXO, or OCXO can be used as an external oscillator.
6
Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin.
7
Refer to the Reference Input section for details on using an external oscillator.


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