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CDCV850DGGG4 数据表(PDF) 4 Page - Texas Instruments |
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CDCV850DGGG4 数据表(HTML) 4 Page - Texas Instruments |
4 / 20 page CDCV850 2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range: VDDQ, AVDD −0.5 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDDI −0.5 V to 4.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range: VI (except SCLK and SDATA) (see Notes 1 and 2) – 0.5 V to VDDQ + 0.5 V . . . . . . . . . VI (SCLK, SDATA) (see Notes 1 and 2) – 0.5 V to VDDI + 0.5 V . . . . . . . . . . . . . . . . . . . . Output voltage range: VO (except SDATA) (see Notes 1 and 2) – 0.5 V to VDDQ + 0.5 V . . . . . . . . . . . . . . . . . . VO (SDATA) (see Notes 1 and 2) – 0.5 V to VDDQ + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current, IIK (VI < 0 or VI > VDDQ) ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current, IOK (VO < 0 or VO > VDDQ) ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous output current, IO (VO = 0 to VDDQ) ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 3): DGG package 89°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range Tstg – 65°C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 3.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) MIN TYP MAX UNIT Supply voltage VDDQ, AVDD 2.3 2.7 V Supply voltage VDDI (see Note 5) 2.3 3.6 V CLK, CLK, HCSL Buffer only 0 0.24 Low level input voltage V CLK, CLK −0.3 VDDQ − 0.4 V Low level input voltage, VIL FBIN, FBIN VDDQ/2 − 0.18 V SDATA, SCLK 0.3 × VDDI CLK, CLK, HCSL Buffer only 0.66 0.71 High level input voltage V CLK, CLK 0.4 VDDQ + 0.3 V High level input voltage, VIH FBIN, FBIN VDDQ/2 + 0.18 V SDATA, SCLK 0.7 × VDDI DC input signal voltage (see Note 6) –0.3 VDDQ + 0.3 V Differential input signal voltage V (see Note 7) DC CLK, FBIN 0.36 VDDQ + 0.6 V Differential input signal voltage, VID (see Note 7) AC CLK, FBIN 0.2 VDDQ + 0.6 V Input differential pair cross-voltage, VIX (see Note 8) 0.45×(VIH−VIL) 0.55×(VIH−VIL) V High-level output current, IOH −12 mA Low level output current I 12 V Low-level output current, IOL SDATA 3 mA Input slew rate, SR (see Figure 8) 1 4 V/ns SSC modulation frequency 30 33.3 kHz SSC clock input frequency deviation 0 −0.50 kHz Operating free-air temperature, TA −40 85 °C NOTES: 4. Unused inputs must be held high or low to prevent them from floating. 5. All devices on the serial interface bus, with input levels related to VDDI, must have one common supply line to which the pullup resistor is connected to. 6. DC input signal voltage specifies the allowable dc execution of differential input. 7. Differential input signal voltage specifies the differential voltage |VTR − VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. 8. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing. |
类似零件编号 - CDCV850DGGG4 |
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类似说明 - CDCV850DGGG4 |
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