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SI8502-C-GM 数据表(PDF) 4 Page - List of Unclassifed Manufacturers |
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SI8502-C-GM 数据表(HTML) 4 Page - List of Unclassifed Manufacturers |
4 / 37 page Si85xx 4 Preliminary Rev. 0.4 1. Electrical Specifications Table 1. Electrical Specifications TA = –40 to +125 ºC (typical specified at 25 ºC), VDD = 3 V (±10%) to 5 V (±10%), f = 400 kHz, unless specified Parameter Conditions Min Typ Max Unit Supply Voltage (VDD) 2.7 — 5.5 V Supply Current Fully enabled, input frequency = 1 MHz — 4 7 mA Undervoltage Lockout (VUVLO) 2.1 2.3 2.5 V Undervoltage Lockout Hysteresis (VHYST) — 100 — mV Logic Input HIGH Level MODE, R1, R2, R3, R4 inputs (TTL compatible) 2.0 — — V Logic Input LOW Level — — 0.8 V Reset Time (tR) Time for 5% initial accuracy 150 — — ns Reset Time Resistor Range1 15 — 2500 k R1, R2, R3, R4 Input Rise Time (tRR) — — 30 ns R1, R2, R3, R4 Input Fall Time (tFR) — — 30 ns Measurement Watchdog Timeout (tWD) 30 50 80 µs Series Input Resistance Measured from IIN to IOUT — 1.3 — m Series Inductance Measured from IIN to IOUT — 2 — nH Input/Output Delay1 OUT, OUT1, OUT2 delay relative to input — 150 200 ns Start-Up Self-Cal Delay (tCAL) 1 Time from VDD = VUVLO + VHYST to cal complete — 150 200 µs Input Common Mode Voltage Range (dc) 1 4x4 mm QFN 1000 — — VRMS SOIC-20 5000 — — VRMS Operating Input Frequency Range (f)1 50 — 1000 kHz DC Power Supply Rejection Ratio — 40 — db Sensitivity @ VDD = 3 V Si8501/11/17 — 404 — mV/A Si8502/12/18 — 202 — mV/A Si8503/13/19 — 101 — mV/A Sensitivity @ VDD = 5 V Si8501/11/17 — 392 — mV/A Si8502/12/18 — 196 — mV/A Si8503/13/19 — 98 — mV/A Notes: 1. Guaranteed by design and/or characterization. 2. Maximum output load is not recommended to exceed 200 pF and 5 k . 3. Production tested at 400 kHz (50% duty cycle) at VDD = 3.3 V. 4. See "2.4. Total Measurement Error" on page 11 for more information. |
类似零件编号 - SI8502-C-GM |
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类似说明 - SI8502-C-GM |
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