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CS493292-CL 数据表(PDF) 5 Page - Cirrus Logic |
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CS493292-CL 数据表(HTML) 5 Page - Cirrus Logic |
5 / 86 page CS49300 Family DSP DS339PP4 5 Figure 38. Fast Autoboot Sequence Using GFABT Codes ...............................................................60 Figure 39. Performing a Reset ..........................................................................................................62 Figure 40. Non-Paged Memory .........................................................................................................64 Figure 41. Example Contents of a Paged 32 Kilobytes External Memory (Total 256 Kilobytes) .......64 Figure 42. CDB49300-MEMA.0 Daughter Card for the CDB4923/30-REV-A.0 ................................66 Figure 43. I2S Format ........................................................................................................................68 Figure 44. Left Justified Format (Rising Edge Valid SCLK) ...............................................................68 Figure 45. Multichannel Format .........................................................................................................68 LIST OF TABLES Table 1. PLL Filter Component Values .............................................................................................. 25 Table 2. Host Modes .......................................................................................................................... 32 Table 3. SPI Communication Signals................................................................................................. 33 Table 4. I2C® Communication Signals ............................................................................................. 35 Table 5. Parallel Input/Output Registers ............................................................................................ 42 Table 6. Intel Mode Communication Signals...................................................................................... 43 Table 7. Motorola Mode Communication Signals .............................................................................. 45 Table 8. Memory Interface Pins ......................................................................................................... 49 Table 9. Boot Write Messages ........................................................................................................... 52 Table 10. Boot Read Messages......................................................................................................... 52 Table 11. Reduced Autoboot Times using GFABT8.LD, GFABT6.LD, and GFABT4.LD on a CS493264-CL Rev. G DSP........................................................................................................ 59 Table 12. Memory Requirements for Example 5.1, 6.1 and 7.1 Channel Systems ........................... 63 Table 13. Digital Audio Input Port ...................................................................................................... 68 Table 14. Compressed Data Input Port.............................................................................................. 69 Table 15. Digital Audio Output Port.................................................................................................... 70 Table 16. MCLK/SCLK Master Mode Ratios...................................................................................... 71 Table 17. Output Channel Mapping ................................................................................................... 71 Table 18. Input Data Type Configuration (Input Parameter A)............................................................................................................................ 73 Table 19. Input Data Format Configuration (Input Parameter B)............................................................................................................................ 73 Table 20. Input SCLK Polarity Configuration (Input Parameter C) ........................................................................................................................... 75 Table 21. Input FIFO Setup Configuration (Input Parameter D) ........................................................................................................................... 75 Table 22. Output Clock Configuration (Parameter A)..................................................................................................................................... 76 Table 23. Output Data Format Configuration (Parameter B)..................................................................................................................................... 76 Table 24. Output MCLK Configuration (Parameter C) .................................................................................................................................... 77 Table 25. Output SCLK Configuration (Parameter D) .................................................................................................................................... 77 Table 26. Output SCLK Polarity Configuration (Parameter E)..................................................................................................................................... 77 Table 27. Example Values to be Sent to CS493XX After Download or Soft Reset ........................... 79 |
类似零件编号 - CS493292-CL |
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类似说明 - CS493292-CL |
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