VA+, VD+ = 5V

Parameter

Symbol

Min

Typ

Max

Units

CLKIN Period

(Note 18,24)

0.5

-

10

µs

CLKIN Low Time

200

-

-

ns

CLKIN High Time

200

-

-

ns

Crystal Frequency

(Note 24, 25)

0.9

1.6

2.0

MHz

SLEEP Rising to Oscillator Stable

(Note 26)

-

-

20

-

ms

RST Pulse Width

150

-

-

ns

RST to STBY Falling

-

100

-

ns

RST Rising to STBY Rising

-

2,882,040

-

CH1/2 Edge to TRK1, TRK2 Rising

(Note 27)

-80

-

ns

CH1/2 Edge to TRK1, TRK2 Falling

(Note 27)

-

-

ns

HOLD to SSH Falling

(Note 28)

-60

ns

HOLD to TRK1, TRK2, Falling

(Note 28)

-

ns

HOLD to TRK1, TRK2, SSH Rising

(Note 28)

-

120

-

ns

HOLD Pulse Width

(Note 29)

-

ns

HOLD to CH1/2 Edge

(Note 28)

15

-

ns

HOLD Falling to CLKIN Falling

(Note 29)

55

-

1tclk+10

ns

Note:

24. Minimum CLKIN period is 0.625

µs in FRN mode (20 kHz sample rate). At temperatures >+85 °C,

and with clock frequencies <1.6 MHz, analog performance may be degraded.

25. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency

is 1.6 MHz in FRN mode (20 kHz sample rate).

26. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 M

Ω parallel resistor (see Figure 8).

27. These times are for FRN mode.

28. SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge

29. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must

be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN

after HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse width may be as

narrow as 150 ns for all CLKIN frequencies if CLKIN falls 55 ns after HOLD falls. This

CS5102A

DS45F2

7