CS4391

DS335PP3

3

Serial Audio Data - SDATA ...........................................................................................21

Serial Clock - SCLK ......................................................................................................22

Left / Right Clock - LRCK ..............................................................................................22

Master Clock - MCLK ....................................................................................................22

Mode Select - M3, M2, M1 and M0 (Stand-alone Mode) .............................................22

Mode Select - M3 (Control Port Mode) ........................................................................22

Serial Control Interface Clock - SCL/CCLK (Control Port Mode) .................................23

Serial Control Data I/O - SDA/CDIN (Control Port Mode) .............................................23

Address Bit / Chip Select - AD0 / CS (Control Port Mode)...........................................23

Positive Voltage Reference - FILT+ ..............................................................................23

Common Mode Voltage - CMOUT ................................................................................23

Channel A and Channel B Mute Control - AMUTEC and BMUTEC .............................23

Differential Analog Output - AOUTB+, AOUTB- and AOUTA+, AOUTA-......................24

Analog Ground - AGND ................................................................................................24

Analog Power - VA ........................................................................................................24

6. PIN DESCRIPTION - DSD MODE ....................................................................................25

DSD Audio Data - DSD_A and DSD_B.........................................................................25

DSD Mode - DSD_Mode ...............................................................................................25

Master Clock - MCLK ....................................................................................................25

DSD Serial Clock - DSD_SCLK ...................................................................................25

7. APPLICATIONS .............................................................................................................. .32

7.1 Recommended Power-up Sequence for Hardware Mode ....................................32

7.2 Recommended Power-up Sequence and Access to Control Port Mode ..............32

7.3 Analog Output and Filtering ..................................................................................32

8. CONTROL PORT INTERFACE ........................................................................................33

8.1 SPI Mode ..............................................................................................................33

8.2 I2C Mode ..............................................................................................................33

9. PARAMETER DEFINITIONS ...........................................................................................37

Total Harmonic Distortion + Noise (THD+N) .................................................................37

Dynamic Range.............................................................................................................37

Interchannel Isolation ....................................................................................................37

Interchannel Gain Mismatch .........................................................................................37

Gain Error..................................................................................................................... .37

Gain Drift .......................................................................................................................37

10. REFERENCES ...............................................................................................................37

11. PACKAGE DIMENSIONS

...........................................................................................38