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CS5106 数据表(PDF) 9 Page - Cherry Semiconductor Corporation |
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CS5106 数据表(HTML) 9 Page - Cherry Semiconductor Corporation |
9 / 12 page 9 Figure 1: Startup waveforms. Voltage and Current Ramp PWM Comparator Inputs (VFB1,2 and RAMP1,2 leads) C10 and C11 are the PWM comparators for the auxiliary and main supplies. The feedback voltage (VFB) is divided by three and compared with a linear, voltage representa- tion of the current in the primary side of the transformer (RAMP). When the output of the feedback comparator goes ÔhighÕ, a reset signal is sent to the PWM flip-flop and the GATE driver is driven ÔlowÕ. A 130mV offset on the RAMP leads allows the drivers to go to 0% duty cycle in the presence of light loads. Feedback Voltage for GATE1 Driver (VFB1) Typically the output of the auxiliary error amplifier (A1) is tied to VFB1. The VSS output is programmed to 12V by a 10:1 resistive divider on the negative input of the error amplifier and a fixed 1.2V reference on the positive input of the error amplifier. Pulse by Pulse Over Current Protection and Hiccup Mode (ILIM1,2 leads) C12 and C13 are the pulse by pulse current limit compara- tors for the auxiliary and main supplies. When the current in the primary side of the transformer increases such that the voltage across the current sense resistor exceeds 1.2V nominal, the output of the current limit comparator goes ÔhighÕ and a reset signal is sent to the PWM flip-flop and the GATE driver is driven ÔlowÕ. C16 and C17 are the second threshold, pulse by pulse cur- rent limit comparators for the auxiliary and main supplies. If the current in the primary side of the transformer increases so quickly that the current sense voltage is not limited by C12 or C13 and the voltage across the current sense resistor exceeds 1.4V, the second threshold compara- tor will trip a delay circuit and force the GATE driver stage to go low and stay low for the next two clock cycles. Undervoltage and Overvoltage Thresholds C5 and C8 are the undervoltage and overvoltage detection comparators. Typically, these inputs are tied across the middle resistor in a three resistor divider with the top resistor to VIN and bottom resistor to Ground. The under voltage comparator has 200mV of built in hysteresis with respect to a direct input on the UVSD lead. The under volt- age comparator has its positive input referenced to 5V while the over voltage comparator has its negative input referenced to 5V. The output of both comparators are ORed at (G4) with the over current and enable inputs. The output of G4 feeds the input to the fault latch (F2). PROGRAM and ENABLE Leads The PROGRAM lead controls the polarity of the ENABLE lead. If the PROGRAM lead is ÔhighÕ or floating, the GATE outputs will go low if the ENABLE input is tied ÔhighÕ or floating. If the PROGRAM lead is tied low, the GATE out- puts will go low if the ENABLE input is tied ÔlowÕ. If the part is then enabled after switching the outputs low, the part will restart according to the procedure outlined in the ÒStartupÓ section. FAULT Logic If a VREF, UVSD or OVSD fault occurs at any time, G4 resets the fault latch (F2). RUN1 goes low and all gate drivers cease switching and return to their ÔlowÕ state. When RUN1 goes low, the output of the auxiliary op-amp (A1) discharges the soft start capacitor and holds it low while RUN1 is low. If the fault condition is removed before the OUVDELAY timer is tripped, the IC will restart the power supplies when VSS < 1.4V. If the OUVDELAY timer trips, the power supply must be restarted as explained in the following section. Output Undervoltage Delay Timer for the Main and Auxiliary Regulated Outputs C7 and C4 are the output under voltage monitor compara- tors for the auxiliary and main supplies. If a regulated out- put drops such that its associated VFB voltage exceeds 4.1V, the output undervoltage monitor comparator goes ÔhighÕ and the OUVDELAY capacitor begins charging from 0V. A timing relation is set up by a 10µA nominal current source, the OUVDELAY capacitor and a 5V fault threshold at the input of C2 (see Figure 2). If any regulated output drops and stays low for the entire charge time of the OUVDELAY capacitor, a fault is triggered and all GATE drivers will go into a low state. Once this fault is triggered, the IC will restart the power supplies only if the OUVDELAY fault is reset and ENABLE or UVSD is toggled while VSS < 1.4V. To reset the OUVDE- LAY fault, both the VFB inputs must be less than 4.1V. In the application circuit shown, VFB1 is brought low by OAOUT when RUN1 stops the oscillators. VFB2 is brought low when VAUXP bleeds down and the VFB2 opto-isolator is no longer powered. Figure 2: OUVDELAY Time vs. OUVDELAY Capacitance CAPACITANCE (nF) 0.01 100 1 0.1 10 1 100 1000 0.1 10 1000 VSS > VCC 7.5V VCC VREF,VREF(OK),RUN1 CLK1 GATE1 RAMP1 VFB1 VSS VFB2 RUN2 CLK2 GATE2 RAMP2 GATE2B Theory of Application: continued |
类似零件编号 - CS5106 |
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类似说明 - CS5106 |
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