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AD7091R-4BRUZ 数据表(PDF) 9 Page - List of Unclassifed Manufacturers

部件名 AD7091R-4BRUZ
功能描述  2-/4-/8-Channel, 1 MSPS, Ultralow Power, 12-Bit ADC in 16-/20-/24-Lead TSSOP
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

AD7091R-4BRUZ 数据表(HTML) 9 Page - List of Unclassifed Manufacturers

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AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. 2-Channel Pin Configuration
Table 5. 2-Channel Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CS
Chip Select Input. When CS is held low, the serial bus enables and CS frames the output data on the SPI.
2
RESET
Reset. Logic input.
3
VDD
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
4
REGCAP
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this output pin separately to
GND using a 2.2 µF capacitor.
5
REFIN/REFOUT
Voltage Reference Output, 2.5 V. Decouple this pin to GND. The typical recommended decoupling capacitor
value is 2.2 µF. The user can either access the internal 2.5 V reference or overdrive the internal reference with
the voltage applied to this pin. The reference voltage range for an externally applied reference is 1.0 V to VDD.
6, 11
GND
Chip Ground. These pins are the ground reference point for all circuitry on the AD7091R-2.
7
MUXOUT
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or buffering is
required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the conditioning network to the
ADCIN pin.
8
VIN0
Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF.
9
VIN1
Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF.
10
ADCIN
ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or buffering is required,
tie this pin directly to the MUXOUT pin; otherwise tie the input of the conditioning network to the MUXOUT pin.
12
SDI
Serial Data Input Bus. This input provides the data written to the on-chip control registers. Data clocks into the
registers on the falling edge of the SCLK input. Provide data most significant bits (MSB) first.
13
SDO
Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input, and 13 SCLK cycles are required to access the data. The data is
provided MSB first.
14
SCLK
Serial Clock. This pin acts as the serial clock input.
15
CONVST
Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the track-and-hold
mode into hold mode and initiates a conversion.
16
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
Connect decoupling capacitors between VDRIVE and GND. The typical recommended values are 10 µF and
0.1 µF. The voltage range on this pin is 1.8 V to 5.25 V and may be different from the voltage range at VDD but
must never exceed it by more than 0.3 V.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD7091R-2
TOP VIEW
(Not to Scale)
RESET
VDD
REGCAP
MUXOUT
GND
CS
VIN0
CONVST
SCLK
SDO
ADCIN
GND
SDI
VIN1
VDRIVE
REFIN/REFOUT
Rev. 0 | Page 8 of 40


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