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AD843 数据表(PDF) 9 Page - Analog Devices |
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AD843 数据表(HTML) 9 Page - Analog Devices |
9 / 12 page AD843 REV. D –9– SAMPLE-AND-HOLD AMPLIFIER CIRCUITS A Fast Switching Sample & Hold Circuit A sample-and-hold circuit possessing short acquisition time and low aperture delay can be built using an AD843 and discrete JFET switches. The circuit of Figure 25 employs five n-channel JFETs (with turn-on times of 35 ns) and an AD843 op amp (which can settle to 0.01% in 135 ns). The circuit has an aper- ture delay time of 50 ns and an acquisition time of 1 µs or less. This circuit is based on a noninverting open loop architecture, using a differential hold capacitor to reduce the effects of pedes- tal error. The charge that is removed from CH1 by Q2 and Q3 is offset by the charge removed from CH2 by Q4 and Q5. This circuit can tolerate low hold capacitor values (approximately 100 pF), which improve acquisition time, due to the small gate- to-drain capacitance of the discrete JFETs. Although pedestal error will vary with input signal level, making trimming more difficult, the circuit has the advantages of high bandwidth and short acquisition times. In addition, it will exhibit some nonlinearity because both amplifiers are operating with a com- mon-mode input. Amplifier A2, however, contributes less than 0.025% linearity error, due to its 72 dB common-mode rejec- tion ratio. To make sure the circuit accommodates a wide ±10 V input range, the gates of the JFETs must be connected to a potential near the –15 V supply. The level-shift circuitry (diode D3, PNP transistor Q7, and NPN transistor Q6) shifts the TTL level S/H command to provide for an adequate pinch-off voltage for the JFET switches over the full input voltage range. The JFETs Q2, Q3, Q4 and Q5 across the two hold capacitors ensure signal acquisition for all conditions of VIN and VOUT when the circuit switches from the sample to the hold mode. Transistor Q1 provides an extra stage of isolation between the output of amplifier A1 and the hold capacitor CH1. When selecting capacitors for use in a sample-and-hold circuit, the designer should choose those types with low dielectric absorption and low temperature coefficients. Silvered-mica capacitors exhibit low (0 to 100 ppm/ °C) temperature coeffi- cients and will still work in temperatures exceeding 200 °C. It is also recommend that the user test the chosen capacitor to insure that its value closely matches that printed on it since not all capacitors are fully tested by their manufacturers for absolute tolerance. A high speed CB amplifier, A1, follows the input signal. U1, a dual wideband “T” switch, connects the input buffer amp to one of the two output amplifiers while selecting the complemen- tary amplifier to drive the A/D input. For example, when “select” is at logic high, A1 drives CH1, A2 tracks the input sig- nal and the output of A3 is connected to the input of the A/D converter. At the same time, A3 holds an analog value and its output is connected to the input of the A/D converter. When the select command goes to logic LOW, the two output amplifiers alternate functions. Since the input to the A/D converter is the alternated “held” outputs from A1 and A2, the offset voltage mismatch of the two amplifiers will show up as nonlinearity and, therefore, distortion in the output signal. To minimize this, potentiometers can be used to adjust the offsets of the output amplifiers until they are A PING-PONG S/H AMPLIFIER For improved throughput over the circuit of Figure 25, a “ping- pong” architecture may be used. A ping-pong circuit overcomes some of the problems associated with high speed S/H amplifiers by allowing the use of a larger hold capacitor for a given sample rate: this will reduce the associated feedthrough, droop and ped- estal errors. Figure 26 illustrates a simple, four-chip ping-pong sample-and- hold amplifier circuit. This design increases throughput by using one channel to acquire a new sample while another channel holds the previous sample. Instead of having to reacquire the signal when switching from hold to sample mode, it alternately connects the outputs from Channel 1 or from Channel 2 to the A/D converter. In this case, the throughput is the slew rate and settling time of the output amplifiers, A2 and A3. Figure 25. A Fast Switching Sample-and-Hold Amplifier |
类似零件编号 - AD843 |
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类似说明 - AD843 |
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