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AD2S80ATE883B 数据表(PDF) 3 Page - Analog Devices |
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AD2S80ATE883B 数据表(HTML) 3 Page - Analog Devices |
3 / 16 page Parameter Conditions Min Typ Max Unit DATA LOAD Sense Internally Pulled High (100 k Ω) 150 300 ns to VS. Logic LO Allows Data to be Loaded into the Counters from the Data Lines BUSY 3 Sense Logic HI When Position O/P Changing Width 200 600 ns Load Use Additional Pull-Up 1 LSTTL DIRECTION 3 Sense Logic HI Counting Up Logic LO Counting Down Max Load 3 LSTTL RIPPLE CLOCK 3 Sense Logic HI All 1s to All 0s All 0s to All 1s Width Dependent on Input Velocity 300 Reset Before Next Busy Load 3 LSTTL DIGITAL INPUTS High Voltage, VIH INHIBIT, ENABLE 2.0 V DB1–DB16, Byte Select ±V S = ±10.8 V, V L = 5.0 V Low Voltage, VIL INHIBIT, ENABLE 0.8 V DB1–DB16, Byte Select ±V S = ±13.2 V, V L = 5.0 V DIGITAL INPUTS High Current, IIH INHIBIT, ENABLE 100 µA DB1–DB16 ±V S = ±13.2 V , V L = 5.5 V Low Current, IIL INHIBIT, ENABLE 100 µA DB1–DB16, Byte Select ±V S = ±13.2 V, V L = 5.5 V DIGITAL INPUTS Low Voltage, VIL ENABLE = HI 1.0 V SC1, SC2, Data Load ±V S = ±12.0 V, V L = 5.0 V Low Current, IIL ENABLE = HI –400 µA SC1, SC2, Data Load ±V S = ±12.0 V, V L = 5.0 V DIGITAL OUTPUTS High Voltage, VOH DB1–DB16 2.4 V RIPPLE CLK, DIR ±V S = ±12.0 V, V L = 4.5 V IOH = 100 µA Low Voltage, VOL DB1–DB16 0.4 V RIPPLE CLK, DIR ±V S = ±12.0 V, V L = 5.5 V IOL = 1.2 mA THREE-STATE LEAKAGE DB1–DB16 Only Current IL ±V S = ±12.0 V, V L = 5.5 V ±100 µA VOL = 0 V ±V S = ±12.0 V, V L = 5.5 V ±100 µA VOH = 5.0 V NOTES 1Refer to small signal bandwidth. 2Output offset dependent on value for R6. 3Refer to timing diagram. Specifications subject to change without notice. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. AD2S80A REV. B –3– |
类似零件编号 - AD2S80ATE883B |
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类似说明 - AD2S80ATE883B |
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