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AD2S80ASE883B 数据表(PDF) 6 Page - Analog Devices |
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AD2S80ASE883B 数据表(HTML) 6 Page - Analog Devices |
6 / 16 page AD2S80A REV. B –6– CONNECTING THE CONVERTER The power supply voltages connected to +VS and –VS pins should be +12 V dc and –12 V dc and must not be reversed. The voltage applied to VL can be 5 V dc to +VS. It is recommended that the decoupling capacitors are connected in parallel between the power lines +VS, –VS and ANALOG GROUND adjacent to the converter. Recommended values are 100 nF (ceramic) and 10 µF (tantalum). Also capacitors of 100 nF and 10 µF should be connected between +VL and DIGITAL GROUND adjacent to the converter. When more than one converter is used on a card, then separate decoupling capacitors should be used for each converter. The resolver connections should be made to the SIN and COS inputs, REFERENCE INPUT and SIGNAL GROUND as shown in Figure 7 and described in section “CONNECTING THE RESOLVER.” The two signal ground wires from the resolver should be joined at the SIGNAL GROUND pin of the converter to minimize the coupling between the sine and cosine signals. For this reason it is also recommended that the resolver is connected using indi- vidually screened twisted pair cables with the sine, cosine and reference signals twisted separately. SIGNAL GROUND and ANALOG GROUND are connected internally. ANALOG GROUND and DIGITAL GROUND must be connected externally. The external components required should be connected as shown in Figure 1. CONVERTER RESOLUTION Two major areas of the AD2S80A specification can be selected by the user to optimize the total system performance. The reso- lution of the digital output is set by the logic state of the inputs SC1 and SC2 to be 10, 12, 14, or 16 bits; and the dynamic characteristics of bandwidth and tracking rate are selected by the choice of external components. The choice of the resolution will affect the values of R4 and R6 which scale the inputs to the integrator and the VCO respectively (see section COMPONENT SELECTION). If the resolution is changed, then new values of R4 and R6 must be switched into the circuit. Note: When changing resolution under dynamic conditions, do it when the BUSY is low, i.e., when Data is not changing. A1 A2 SEGMENT SWITCHING R-2R DAC A3 OUTPUT DATA LATCH PHASE SENSITIVE DETECTOR DEMOD I/P DEMOD O/P INTEGRATOR O/P AD2S80A C2 HF FILTER R1 C1 C3 R3 VCO + DATA TRANSFER LOGIC R4 INTEGRATOR I/P R9 R8 –12V +12V OFFSET ADJUST C4 C5 R5 AC ERROR O/P REFERENCE I/P BANDWIDTH SELECTION R6 R7 C6 TRACKING RATE SELECTION VELOCITY SIGNAL VCO I/P SC1 SC2 DATA LOAD 16-BIT UP/DOWN COUNTER ENABLE 16 DATA BITS BYTE SELECT 5V DIG GND BUSY DIRN INHIBIT SIN SIG GND COS GND RIPPLE CLK +12V –12V R2 Figure 1. AD2S80A Connection Diagram |
类似零件编号 - AD2S80ASE883B |
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类似说明 - AD2S80ASE883B |
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