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CAT28C17AN-20T 数据表(PDF) 7 Page - Catalyst Semiconductor |
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CAT28C17AN-20T 数据表(HTML) 7 Page - Catalyst Semiconductor |
7 / 8 page CAT28C17A 7 Doc. No. 25034-00 2/98 ADDRESS CE WE OE I/O7 DIN = X DOUT = X DOUT = X tOE tOEH tWC tOES Byte Write A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. Figure 5. Byte Write Cycle [CE Controlled] ADDRESS CE OE WE RDY/BUSY tAS DATA IN DATA VALID tAH tWC tOEH tDH tDS tOES tDL tCH tCS tCW tDB DATA OUT HIGH-Z Figure 6. DATA Polling 28C17A F08 5091 FHD F07 DATA Polling DATA polling is provided to indicate the completion of a byte write cycle. Once a byte write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0–I/O6 are indeter- minate) until the programming cycle is complete. Upon completion of the self-timed byte write cycle, all I/O’s will output true data during a read cycle. |
类似零件编号 - CAT28C17AN-20T |
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类似说明 - CAT28C17AN-20T |
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