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CAT24C041JI-45TE13 数据表(PDF) 3 Page - Catalyst Semiconductor |
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CAT24C041JI-45TE13 数据表(HTML) 3 Page - Catalyst Semiconductor |
3 / 12 page CAT24CXX1/XX2 3 Advanced Doc. No. 25079-00 1/98 M-1 A.C. CHARACTERISTICS VCC=2.7V to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits Symbol Parameter VCC=2.7V - 6V VCC=4.5V - 5.5V Min. Max. Min. Max. Units FSCL Clock Frequency 100 400 kHz TI(1) Noise Suppression Time 200 200 ns Constant at SCL, SDA Inputs tAA SCL Low to SDA Data Out 3.5 1 µs and ACK Out tBUF(1) Time the Bus Must be Free Before 4.7 1.2 µs a New Transmission Can Start tHD:STA Start Condition Hold Time 4 0.6 µs tLOW Clock Low Period 4.7 1.2 µs tHIGH Clock High Period 4 0.6 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs (for a Repeated Start Condition) tHD:DAT Data In Hold Time 0 0 ns tSU:DAT Data In Setup Time 50 50 ns tR(1) SDA and SCL Rise Time 1 0.3 µs tF(1) SDA and SCL Fall Time 300 300 ns tSU:STO Stop Condition Setup Time 4 0.6 µs tDH Data Out Hold Time 100 100 ns Power-Up Timing(1)(2) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Write Cycle Limits Symbol Parameter Min. Typ. Max Units tWR Write Cycle Time 10 ms The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. |
类似零件编号 - CAT24C041JI-45TE13 |
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类似说明 - CAT24C041JI-45TE13 |
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