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CAT25C03/05/09/17/33

Doc. No. 25068-00 2/98

Advanced

FUNCTIONAL DESCRIPTION

The CAT25C03/05/09/17/33 supports the SPI bus data

transmission protocol. The synchronous Serial Periph-

eral Interface (SPI) helps the CAT25C03/05/09/17/33 to

interface directly with many of today’s popular

microcontrollers. The CAT25C03/05/09/17/33 contains

an 8-bit instruction register. (The instruction set and the

operation codes are detailed in the instruction set table)

After the device is selected with

CS going low, the first

byte will be received. The part is accessed via the SI pin,

with data being clocked in on the rising edge of SCK.

The first byte contains one of the six op-codes that define

the operation to be performed.

PIN DESCRIPTION

SI: Serial Input

SI is the serial data input pin. This pin is used to input all

opcodes, byte addresses, and data to be written to the

25C03/05/09/17/33. Input data is latched on the rising

edge of the serial clock.

SO: Serial Output

SO is the serial data output pin. This pin is used to

transfer data out of the 25C03/05/09/17/33. During a

read cycle, data is shifted out on the falling edge of the

serial clock.

SCK: Serial Clock

SCK is the serial clock pin. This pin is used to synchro-

nize the communication between the microcontroller

and the 25C03/05/09/17/33. Opcodes, byte addresses,

or data present on the SI pin are latched on the rising

edge of the SCK. Data on the SO pin is updated on the

falling edge of the SCK.

CS

CS

CS

CS

CS: Chip Select

CS is the Chip select pin. CS low enables the CAT25C03/

05/09/17/33 and

CS high disables the CAT25C03/05/

09/17/33.

CS high takes the SO output pin to high

impedance and forces the devices into a Standby Mode

(unless an internal write operation is underway)

The

CAT25C03/05/09/17/33 draws ZERO current in the

Standby mode. A high to low transition on

CS is required

prior to any sequence being initiated. A low to high

transition on

CS after a valid write sequence is what

initiates an internal write cycle.

WP

WP

WP

WP

WP: Write Protect

WP is the Write Protect pin. The Write Protect pin will

allow normal read/write operations when held high.

When

WP is tied low, all write operations to the device

are inhibited.

WP going low while CS is still low will

interrupt a write to the status register. If the internal write

cycle has already been initiated,

WP going low will have

no effect on any write operation to the status register.

HOLD

HOLD

HOLD

HOLD

HOLD: Hold

HOLD is the HOLD pin. The HOLD pin is used to pause

transmission to the CAT25C03/05/09/17/33 while in the

middle of a serial sequence without having to re-transmit

entire sequence at a later time. To pause,

HOLD must be

Instruction

Opcode

Operation

WREN

0000 0110

Enable Write Operations

WRDI

0000 0100

Disable Write Operations

RDSR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register

READ

Read Data from Memory

WRITE

Write Data to Memory

INSTRUCTION SET

Note:

(1) X=O for 25C03, 25C09, 25C17 and 25C33. X=A8 for 25C05

(2) This parameter is tested initially and after a design or process change that affects the parameter.

Symbol

Parameter

Max.

Units

Power-up to Read Operation

1

ms

Power-up to Write Operation

1

ms