数据搜索系统,热门电子元器件搜索 |
|
DAC1220 数据表(PDF) 10 Page - Burr-Brown (TI) |
|
|
DAC1220 数据表(HTML) 10 Page - Burr-Brown (TI) |
10 / 14 page 10 ® DAC1220 SLEEP MODE The Sleep Mode is entered after the bit combination 10 has been written to the CMR Operation Mode bits (MD1 and MD0). This mode ends when these bits are changed to a value other than 10. Communication with the DAC1220 can continue during Sleep Mode. When a new mode (other than Sleep) has been entered, the DAC1220 will execute a very brief internal power-up sequence of the analog and digital circuitry. In addition, the settling of the external VREF and other circuitry must be taken into account to determine the amount of time required to resume normal operation. The output is turned off in sleep mode. SERIAL INTERFACE The DAC1220 includes a flexible serial interface which can be connected to microcontrollers and digital signal proces- sors in a variety of ways. Along with this flexibility, there is also a good deal of complexity. This section describes the trade-offs between the different types of interfacing methods in a top-down approach—starting with the overall flow and control of serial data, moving to specific interface examples, and then providing information on various issues related to the serial interface. t 1 t 3 t 4 t 2 t 2 SCLK Reset On Falling Edge FIGURE 3. Resetting the DAC1220. t1: > 512 • tXIN < 800 • tXIN t2: > 10 • tXIN t3: > 1024 • tXIN < 1800 • tXIN t4: ≥ 2048 • tXIN < 2400 • tXIN Reset, Power-On Reset and Brown-Out The DAC1220 contains an internal power-on reset circuit. If the power supply ramp rate is greater than 50mV/ms, this circuit will be adequate to ensure the device powers up correctly. Due to oscillator settling considerations, commu- nication to and from the DAC1220 should not occur for at least 25ms after power is stable. If this requirement cannot be met or if the circuit has brown- out considerations, the timing diagram of Figure 3 can be used to reset the DAC1220. This accomplishes the reset by controlling the duty cycle of the SCLK input. Sleep mode is the default state after power on or reset. The output is high impedance during sleep mode. I/O Recovery If serial communication stops during an instruction or data transfer for longer than 100ms (for fXIN = 2.5MHz), the DAC1220 will reset its serial interface. This will not affect the internal registers. The main controller must not continue the transfer after this event, but must restart the transfer from the beginning. This feature is very useful if the main control- ler can be reset at any point. After reset, simply wait 200ms (for fXIN = 2.5MHz) before starting serial communication. Isolation The serial interface of the DAC1220 provides for simple isolation methods. An example of an isolated two-wire interface is shown in Figure 4. 1 2 3 4 5 6 7 8 DV DD X OUT X IN DGND AV DD DNC DNC DNC SCLK SDIO CS AGND V REF V OUT C 2 C 1 16 15 14 13 12 11 10 9 DAC1220 C 2 12pF C 1 12pF AV DD XTAL V OUT V REF DV DD P1.1 P1.0 8051 Opto Coupler Opto Coupler Isolated Power C 2 C 1 = DGND = AGND = Isolated FIGURE 4. Isolation for Two-Wire Interface |
类似零件编号 - DAC1220 |
|
类似说明 - DAC1220 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |