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TC4468EJD 数据表(PDF) 3 Page - Microchip Technology |
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TC4468EJD 数据表(HTML) 3 Page - Microchip Technology |
3 / 22 page 2002 Microchip Technology Inc. DS21425B-page 3 TC4467/TC4468/TC4469 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† Supply Voltage ...............................................................+20 V Input Voltage ............................. (GND – 5 V) to (VDD + 0.3 V) Package Power Dissipation: (TA ≤ 70°C) PDIP...................................................................800 mW CERDIP .............................................................840 mW SOIC ..................................................................760 mW Package Thermal Resistance: CERDIP RθJ-A ...................................................100°C/W CERDIP RθJ-C.....................................................23°C/W PDIP RθJ-A ..........................................................80°C/W PDIP RθJ-C..........................................................35°C/W SOIC RθJ-A..........................................................95°C/W SOIC RθJ-C..........................................................28°C/W Operating Temperature Range: C Version ................................................... 0°C to +70°C E Version.................................................-40°C to +85°C M Version ..............................................-55°C to +125°C Maximum Chip Temperature....................................... +150°C Storage Temperature Range.........................-65°C to +150°C †Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, TA = +25°C, with 4.5 V ≤ VDD ≤ 18 V. Parameters Sym Min Typ Max Units Conditions Input Logic 1, High Input Voltage VIH 2.4 — VDD V Note 3 Logic 0, Low Input Voltage VIL —— 0.8 V Note 3 Input Current IIN -1.0 — +1.0 µA 0 V ≤ VIN ≤ VDD Output High Output Voltage VOH VDD – 0.025 — — V ILOAD = 100 µA (Note 1) Low Output Voltage VOL — — 0.15 V ILOAD = 10 mA (Note 1) Output Resistance RO —10 15 Ω IOUT = 10 mA, VDD = 18 V Peak Output Current IPK —1.2 — A Continuous Output Current IDC — — 300 mA Single Output — — 500 Total Package Latch-Up Protection Withstand Reverse Current I— 500 — mA 4.5 V ≤ VDD ≤ 16 V Switching Time (Note 1) Rise Time tR — 15 25 nsec Figure 4-1 Fall Time tF — 15 25 nsec Figure 4-1 Delay Time tD1 — 40 75 nsec Figure 4-1 Delay Time tD2 — 40 75 nsec Figure 4-1 Power Supply Power Supply Current IS —1.5 4 mA Power Supply Voltage VDD 4.5 — 18 V Note 2 Note 1: Totem pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device. Switching times are ensured by design. 2: When driving all four outputs simultaneously in the same direction, VDD will be limited to 16 V. This reduces the chance that internal dv/dt will cause high-power dissipation in the device. 3: The input threshold has approximately 50 mV of hysteresis centered at approximately 1.5 V. Input rise times should be kept below 5µsec to avoid high internal peak currents during input transitions. Static input levels should also be maintained above the maximum, or below the minimum, input levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device. |
类似零件编号 - TC4468EJD |
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类似说明 - TC4468EJD |
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