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74ALVCH16901DGGRE4 数据表(PDF) 2 Page - Texas Instruments |
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74ALVCH16901DGGRE4 数据表(HTML) 2 Page - Texas Instruments |
2 / 14 page SN74ALVCH16901 18BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010F − JULY 1995 − REVISED SEPTEMBER 2004 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The A and B I/Os and APAR and BPAR inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. Function Tables FUNCTION† INPUTS OUTPUT CLKENAB OEAB LEAB CLKAB A OUTPUT B X H X X X Z X LH X L L X LH X H H H LL X X B0‡ L LL ↑ LL L LL ↑ HH L LL L X B0‡ L L L H X B0§ † A-to-B data flow is shown; B-to-A flow is similar, but uses OEBA, LEBA, and CLKENBA. ‡ Output level before the indicated steady-state input conditions were established § Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low PARITY ENABLE INPUTS OPERATION OR FUNCTION SEL OEBA OEAB OPERATION OR FUNCTION L H L Parity is checked on port A and is generated on port B. L L H Parity is checked on port B and is generated on port A. L H H Parity is checked on port B and port A. L L L Parity is generated on port A and B if device is in FF mode. H L L Parity functions are disabled; QA data to B, QB data to A H LH Parity functions are disabled; device acts as a standard QB data to A H HL device acts as a standard 18-bit registered transceiver. QA data to B H H H 18-bit registered transceiver. Isolation |
类似零件编号 - 74ALVCH16901DGGRE4 |
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类似说明 - 74ALVCH16901DGGRE4 |
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