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AD5336 数据表(PDF) 1 Page - Analog Devices |
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AD5336 数据表(HTML) 1 Page - Analog Devices |
1 / 24 page 2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs AD5346/AD5347/AD5348 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. FEATURES AD5346: octal 8-bit DAC AD5347: octal 10-bit DAC AD5348: octal 12-bit DAC Low power operation: 1.4 mA (max) @ 3.6 V Power-down to 120 nA @ 3 V, 400 nA @ 5 V Guaranteed monotonic by design over all codes Rail-to-rail output range: 0 V to VREF or 0 V to 2 × VREF Power-on reset to 0 V Simultaneous update of DAC outputs via LDAC pin Asynchronous CLR facility Readback Buffered/unbuffered reference inputs 20 ns WR time 38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging Temperature range: –40°C to +105°C APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Optical networking Automatic test equipment Mobile communications Programmable attenuators Industrial process control GENERAL DESCRIPTION The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit DACs, operating from a 2.5 V to 5.5 V supply. These devices incorporate an on-chip output buffer that can drive the output to both supply rails, and also allow a choice of buffered or unbuffered reference input. The AD5346/AD5347/AD5348 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. A readback feature allows the internal DAC registers to be read back through the digital port. The GAIN pin on these devices allows the output range to be set at 0 V to VREF or 0 V to 2 × VREF. Input data to the DACs is double-buffered, allowing simultane- ous update of multiple DACs in a system using the LDAC pin. An asynchronous CLR input is also provided, which resets the contents of the input register and the DAC register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device. All three parts are pin compatible, which allows users to select the amount of resolution appropriate for their application without redesigning their circuit board. FUNCTIONAL BLOCK DIAGRAM INPUT REGISTER DAC REGISTER STRING DAC C STRING DAC A STRING DAC B STRING DAC D STRING DAC E STRING DAC F STRING DAC G STRING DAC H DGND VOUTB VOUTC VOUTD VOUTE VOUTG VOUTH VOUTF VDD POWER-ON RESET VOUTA VREFEF VREFAB PD INTER- FACE LOGIC GAIN DB11 DB0 CS WR A0 A1 CLR LDAC . . . BUF A2 RD VREFGH VREFCD AGND BUFFER BUFFER BUFFER BUFFER BUFFER BUFFER BUFFER BUFFER INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER AD5348 POWER-DOWN LOGIC Figure 1. 1Protected by U.S. Patent No. 5,969,657. |
类似零件编号 - AD5336 |
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类似说明 - AD5336 |
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