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74LVTH125PW 数据表(PDF) 5 Page - NXP Semiconductors |
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74LVTH125PW 数据表(HTML) 5 Page - NXP Semiconductors |
5 / 16 page 74LVT_LVTH125_6 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 06 — 6 March 2006 5 of 16 Philips Semiconductors 74LVT125; 74LVTH125 3.3 V quad buffer; 3-state 8. Limiting values [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 9. Recommended operating conditions Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +4.6 V VI input voltage [1] −0.5 +7.0 V VO output voltage output in OFF-state or HIGH-state [1] −0.5 +7.0 V IIK input clamping current VI <0V - −50 mA IOK output clamping current VO <0V - −50 mA IO output current output in LOW-state - 128 mA output in HIGH-state - −64 mA Tstg storage temperature −65 +150 °C Tj junction temperature [2] - 150 °C Table 6. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 2.7 - 3.6 V VI input voltage 0 - 5.5 V VIH HIGH-state input voltage 2.0 - - V VIL LOW-state input voltage - - 0.8 V IOH HIGH-state output current - - −32 mA IOL LOW-state output current none - - 32 mA current duty cycle ≤ 50 %; f ≥ 1 kHz --64 mA ∆t/∆V input transition rise and fall rate 0 - 10 ns/V Tamb ambient temperature in free air −40 - +85 °C |
类似零件编号 - 74LVTH125PW |
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类似说明 - 74LVTH125PW |
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