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AM28F256A-200JEB 数据表(PDF) 1 Page - Advanced Micro Devices |
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AM28F256A-200JEB 数据表(HTML) 1 Page - Advanced Micro Devices |
1 / 35 page FINAL Publication# 18879 Rev: C Amendment/+2 Issue Date: May 1998 Am28F256A 256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms DISTINCTIVE CHARACTERISTICS s High performance — Access times as fast as 70 ns s CMOS low power consumption — 30 mA maximum active current — 100 µA maximum standby current — No data retention power consumption s Compatible with JEDEC-standard byte-wide 32-Pin EPROM pinouts — 32-pin PDIP — 32-pin PLCC — 32-pin TSOP s 100,000 write/erase cycles minimum s Write and erase voltage 12.0 V ±5% s Latch-up protected to 100 mA from –1 V to VCC +1 V s Embedded Erase Electrical Bulk Chip-Erase — 1.5 seconds typical chip-erase including pre-programming s Embedded Program — 14 µs typical byte-program including time-out — 0.5 second typical chip program s Command register architecture for microprocessor/microcontroller compatible write interface s On-chip address and data latches s Advanced CMOS flash memory technology — Low cost single transistor memory cell s Embedded algorithms for completely self-timed write/erase operations GENERAL DESCRIPTION The Am28F256A is a 256 K Flash memory organized as 32 Kbytes of 8 bits each. AMD’s Flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. The Am28F256A is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-sys- tem or in sta ndard EPROM programmers. Th e Am28F256A is erased when shipped from the factory. The standard Am28F256A offers access times as fast as 70 ns, allowing operation of high-speed micropro- cessors without wait states. To eliminate bus conten- tion, the Am28F256A has separate chip enable (CE#) and output enable (OE#) controls. AMD’s Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F256A uses a command register to manage this functionality, while maintaining a standard JEDEC Flash Standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming. AMD’s Flash technology reliably stores memory con- tents even after 100,000 erase and program cycles. The AMD cell is designed to optimize the erase and programming mechanisms. In addition, the combina- tion of advanced tunnel oxide processing and low inter- nal elec tr ic fields fo r erase a nd programmi ng operations produces reliable cycling. The Am28F256A uses a 12.0 V ±5% V PP high voltage input to perform the erase and programming functions. The highest degree of latch-up protection is achieved with AMD’s proprietary non-epi process. Latch-up pro- tection is provided for stresses up to 100 milliamps on address and data pins from –1 V to VCC +1 V. Embedded Program The Am28F256A is byte programmable using the Embedded Programming algorithm. The Embedded Programming algorithm does not require the system to time-out or verify the data programmed. The typical r o o m te m p e r a t ur e pr ogr a m m i ng tim e o f th e Am28F256A is one half second. Embedded Erase The entire chip is bulk erased using the Embedded Erase algorithm. The Embedded Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are |
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