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AM79C971KCW 数据表(PDF) 2 Page - Advanced Micro Devices |
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AM79C971KCW 数据表(HTML) 2 Page - Advanced Micro Devices |
2 / 265 page 2 Am79C971 s Supports up to 1 Megabyte (Mbyte) optional Boot PROM and Flash for diskless node application s Look-Ahead Packet Processing (LAPP) data handling technique reduces system overhead by allowing protocol analysis to begin before the end of a receive frame s Includes Programmable Inter Packet Gap (IPG) to address less network aggressive MAC controllers s Offers the Modified Back-Off algorithm to address the Ethernet Capture Effect s IEEE 1149.1-compliant JTAG Boundary Scan test access port interface and NAND tree test mode for board-level production connectivity test s Implements low-power management for critical battery powered application and green PCs — Includes two power-saving sleep modes (sleep and snooze) — Integrated Magic Packet™ technology support for remote power of networked PCs s Software compatible with AMD PCnet Family and LANCE/C-LANCE register and descriptor architecture s Compatible with the existing PCnet Family driver/diagnostic software s Available in 160-pin TQFP and 176-pin TQFP packages GENERAL DESCRIPTION The Am79C971 controller is a single-chip 32-bit full-du- plex, 10/100-Megabit per second (Mbps) highly- integrated Ethernet system solution, designed to address high-performance system application require- ments. It is a flexible bus mastering device that can be used in any application, including network-ready PCs and bridge/router designs. The bus master architecture provides high data throughput in the system and low CPU and system bus utilization. The Am79C971 con- troller is fabricated with AMD’s advanced low-power Complementary Metal Oxide Semiconductor (CMOS) process to provide low operating and standby current for power sensitive applications. The Am79C971 controller is a complete Ethernet node integrated into a single VLSI device. It contains a bus interface unit, a Direct Memory Access (DMA) Buffer Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)- compliant Media Access Controller (MAC), a large Transmit FIFO and a large Receive FIFO, SRAM- based FIFO extension with support for up to 128K bytes of external frame buffering, an IEEE 802.3u-com- pliant MII, an IEEE 802.3-compliant Twisted-Pair Trans- ceiver Media Attachment Unit (10BASE-T MAU), and an IEEE 802.3-compliant Attachment Unit Interface (AUI). Both proprietary full-duplex and IEEE 802.3 compliant half-duplex operation are supported on the MII, AUI, GPSI, and 10BASE-T MAU interfaces. 10- Mbps operation is supported through the MII, AUI, and 10BASE-T MAU interfaces, and 100 Mbps operation is supported through the MII. The 10BASE-T MAU inter- face includes an IEEE 802.3-compliant auto-negotia- tion implementation, which will automatically negotiate between half- and full-duplex with another IEEE 802.3- compliant auto-negotiation 10BASE-T device. The Am79C971 controller is register compatible with the LANCE (Am7990) Ethernet controller, the C- LANCE (Am79C90) Ethernet controller, and all Ether- net controllers in the PCnet Family except ILACC (Am79C900), including the PCnet-ISA controller (Am79C960),PCnet-ISA+ controller (Am79C961), PCnet-ISA II controller (Am79C961A), PCnet-32 con- t r o ller ( A m7 9C9 65) , PCn e t- PC I co ntr o ll er ( A m79 C 97 0) , and PCne t- PCI I I co ntr o ll er (Am79C970A). The Buffer Management Unit supports the LANCE and PCnet descriptor software models. The 32-bit multiplexed bus interface unit provides a direct interface to the PCI local bus, simplifying the design of an Ethernet node in a PC system. The Am79C971 controller provides the complete interface to an Expansion ROM or Flash device allowing add-on card designs with only a single load per PCI bus inter- face pin. With its built-in support for both little and big endian byte alignment, this controller also addresses non-PC applications. The Am79C971 controller’s ad- vanced CMOS design allows the bus interface to be connected to either a +5-V or a +3.3-V signaling envi- ronment. A compliant IEEE 1149.1 JTAG test interface for board-level testing is also provided, as well as a NAND tree test structure for those systems that cannot support the JTAG interface. The Am79C971 controller supports auto-configuration in the PCI configuration space. Additional Am79C971 controller configuration parameters, including the unique IEEE physical address, can be read from an ex- ternal non-volatile memory (EEPROM) immediately fol- lowing system reset. The integrated Manchester encoder/decoder (MEN- DEC) eliminates the need for an external Serial Inter- face Adapter (SIA) in the system. The built-in GPSI allows the MENDEC to be bypassed. |
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类似说明 - AM79C971KCW |
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