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AM7996 数据表(PDF) 9 Page - Advanced Micro Devices

部件名 AM7996
功能描述  IEEE 802.3/Ethernet/Cheapernet Transceiver
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM7996 数据表(HTML) 9 Page - Advanced Micro Devices

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AMD
9
Am7996
LAYOUT CONSIDERATIONS
To protect the transceiver from the environment and to
achieve optimum performance, the Am7996 is designed
to be used with two sets of external components: the
transmitter circuit consisting of components D1, D2, D3,
R7, R8, and C3, and the receiver circuit consisting of
components R5, R6, CL, and CC, (CL is a parasitic ca-
pacitance rather than a discrete component). These two
circuits are shown in both Figure 2 and in Figure 3 re-
spectively. The resistor tolerances for these circuits are
specified as 1% for temperature stability.
The only layout restriction for the transmitter circuit is
that the longest current path from the TXT pin (Pin 12) to
the coaxial cable’s center conductor must be no longer
than 4 inches.
The layout of the receiver circuit, however, is critical. To
minimize parasitic capacitance that can degrade the re-
ceived signal, the external receiver circuit should be iso-
lated from power and ground planes. There must be no
power or ground plane under the area of the PC board
that includes pins 15 through 20, R5, R6, and the con-
nector for the coaxial cable. If a power or ground plane
extends under this area, the receiver will not function
properly due to excessive crosstalk and under- or over-
compensation of the R5, R6 attenuator. Also, the RXT
pin (Pin 16) should be as close to the coaxial cable
connector as possible.
Since there are no severe layout restrictions on the
transmitter circuit, the layout can be simplified by omit-
ting power and ground planes from the whole area on
the right side of the Am7996 as shown in Figure 4-1.
07506E-7
20
RXT
Am7996
TXT
11
R5, R6, R4
C1, C2
D1, D2, D3
R7, R8
C3
Area with no power or ground plane
Coax
Connector
Figure 4-1.
If the above layout rules are followed, the parasitic
capacitance in parallel with R6 will be about 6 pF. This
parasitic capacitance is shown in the schematics as CL
(Note that CL is a parasitic capacitance. Do not add a
discrete capacitor in parallel with R6). The capacitor
labeled CC in the schematics is the total capacitance in
parallel with R5 including parasitic capacitance. The
parasitic component of CC will be about 1 pF. For opti-
mum performance, the ratio of CL to CC should be the
same as the ration of R5 to R6, which is 3 to 1. This
means that an additional 1 pF of capacitance must be
added in parallel with R5.
This additional capacitance can easily be added by
building a parallel-plate capacitor for PC traces right un-
der resistor R5. This capacitor can consist of a 0.200 in.
by 0.200 in. square of conductor on each side of the
board as shown in Figure 4-2 (These dimensions as-
sume that the PC board is made from 0.060 in. thick
G-10 material). The top plate of the capacitor should be
connected to one lead of R5, and the bottom plate
should be connected to the other lead. Figure 4-3 shows
an example of this suggested layout for a four layer
printed circuit board. Note that the component labeling
used in Figure 4-3 is not intended to correspond with the
component labeling used in Figure 2 and Figure 3.
Circuit
Side
Component
Side
0.200 in x 0.200 in
two planes
R5
07506E-8
Figure 4-2.


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