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AD7712AR-REEL7 数据表(PDF) 5 Page - Analog Devices |
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AD7712AR-REEL7 数据表(HTML) 5 Page - Analog Devices |
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5 / 28 page  REV. F AD7712 –5– Limit at TMIN, TMAX Parameter (A, S Versions) Unit Conditions/Comments fCLK IN 4, 5 Master Clock Frequency: Crystal Oscillator or Externally Supplied 400 kHz min AVDD = 5 V ± 5% 10 MHz max For Specified Performance 8 MHz AVDD = 5.25 V to 10.5 V tCLK IN LO 0.4 tCLK IN ns min Master Clock Input Low Time; tCLK IN = 1/fCLK IN tCLK IN HI 0.4 tCLK IN ns min Master Clock Input High Time tr 6 50 ns max Digital Output Rise Time; Typically 20 ns tf 6 50 ns max Digital Output Fall Time; Typically 20 ns t1 1000 ns min SYNC Pulse Width Self-Clocking Mode t2 0 ns min DRDY to RFS Setup Time; t CLK IN = 1/fCLK IN t3 0 ns min DRDY to RFS Hold Time t4 2 tCLK IN ns min A0 to RFS Setup Time t5 0 ns min A0 to RFS Hold Time t6 4 tCLK IN + 20 ns max RFS Low to SCLK Falling Edge t7 7 4 tCLK IN + 20 ns max Data Access Time ( RFS Low to Data Valid) t8 7 tCLK IN/2 ns min SCLK Falling Edge to Data Valid Delay tCLK IN/2 + 30 ns max t9 tCLK IN/2 ns nom SCLK High Pulse Width t10 3 tCLK IN/2 ns nom SCLK Low Pulse Width t14 50 ns min A0 to TFS Setup Time t15 0 ns min A0 to TFS Hold Time t16 4 tCLK IN + 20 ns max TFS to SCLK Falling Edge Delay Time t17 4 tCLK IN ns min TFS to SCLK Falling Edge Hold Time t18 0 ns min Data Valid to SCLK Setup Time t19 10 ns min Data Valid to SCLK Hold Time NOTES 1Guaranteed by design, not production tested. Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 11 to 14. 3The AD7712 is specified with a 10 MHz clock for AV DD voltages of 5 V ± 5%. It is specified with an 8 MHz clock for AV DD voltages greater than 5.25 V and less than 10.5 V. 4CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7712 is not in STANDBY mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 5The AD7712 is production tested with f CLK IN at 10 MHz (8 MHz for AVDD < 5.25 V). It is guaranteed by characterization to operate at 400 kHz. 6Specified using 10% and 90% points on waveform of interest. 7These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. (DVDD = +5 V 5%; AVDD = +5 V or +10 V 3 5%; VSS = 0 V or –5 V 5%; AGND = DGND = 0 V; fCLKIN =10 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.) TIMING CHARACTERISTICS1, 2 |
类似零件编号 - AD7712AR-REEL7 |
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类似说明 - AD7712AR-REEL7 |
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