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AD7712AR-REEL 数据表(PDF) 10 Page - Analog Devices |
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AD7712AR-REEL 数据表(HTML) 10 Page - Analog Devices |
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10 / 28 page  REV. F –10– AD7712 PGA Gain G2 Gl G0 Gain 00 01 (Default Condition after the Internal Power-On Reset) 00 1 2 01 0 4 01 1 8 10 0 16 10 1 32 11 0 64 11 1 128 Channel Selection CH Channel 0AIN1Low Level Input (Default Condition after the Internal Power-On Reset) 1 AIN2 High Level Input Power-Down PD 0Normal Operation (Default Condition after the Internal Power-On Reset) 1 Power-Down Word Length WL Output Word Length 0 16-Bit (Default Condition after Internal Power-On Reset) 1 24-Bit Burnout Current BO 0Off (Default Condition after Internal Power-On Reset) 1On Bipolar/Unipolar Selection (Both Inputs) B/U 0 Bipolar (Default Condition after Internal Power-On Reset) 1 Unipolar Filter Selection (FS11–FS0) The on-chip digital filter provides a sinc 3 (or (sinx/x)3) filter response. The 12 bits of data programmed into these bits deter- mine the filter cutoff frequency, the position of the first notch of the filter, and the data rate for the part. In association with the gain selection, it also determines the output noise (and therefore the effective resolution) of the device. The first notch of the filter occurs at a frequency determined by the relationship filter first notch frequency = (fCLK IN/512)/code where code is the decimal equivalent of the code in bits FS0 to FS11 and is in the range 19 to 2,000. With the nominal fCLK IN of 10 MHz, this results in a first notch frequency range from 9.76 Hz to 1.028 kHz. To ensure correct operation of the AD7712, the value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device. Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I and II and Figure 2 show the effect of the filter notch frequency and gain on the effective resolution of the AD7712. The output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz, then a new word is available at a 50 Hz rate or every 20 ms. If the first notch is at 1 kHz, a new word is avail- able every 1 ms. The settling time of the filter to a full-scale step input change is worst case 4 1/(output data rate). This settling time is to 100% of the final value. For example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is 80 ms max. If the first notch is at 1 kHz, the settling time of the filter to a full-scale input step is 4 ms max. This settling time can be reduced to 3 l/(output data rate) by syn- chronizing the step input change to a reset of the digital filter. In other words, if the step input takes place with SYNC low, the settling time will be 3 l/(output data rate). If a change of channels takes place, the settling time is 3 l/(output data rate) regardless of the SYNC input. The –3 dB frequency is determined by the programmed first notch frequency according to the relationship filter –3 dB frequency = 0.262 first notch frequency. |
类似零件编号 - AD7712AR-REEL |
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类似说明 - AD7712AR-REEL |
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