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U1AFS6003 数据表(PDF) 9 Page - Microsemi Corporation |
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U1AFS6003 数据表(HTML) 9 Page - Microsemi Corporation |
9 / 27 page 9 www.microsemi.com/soc IGLOO PLUS IGLOO PLUS Devices I/Os Per Package IGLOO PLUS Devices AGLP030 AGLP060 AGLP125 System Gates 30,000 60,000 125,000 Typical Equivalent Macrocells 256 512 1,024 VersaTiles(D-flip-flops) 792 1,584 3,120 Flash*FreezeMode(typical,µW) 5 10 16 RAM(1,024bits) — 18 36 4,608-BitBlocks — 4 8 FlashROMKbits(1,024bits) 1 1 1 AES-Protected ISP — Yes Yes Integrated PLL in CCCs1 — 1 1 VersaNetGlobals2 6 18 18 I/OBanks 4 4 4 Maximum User I/Os (packaged device) 120 157 212 Package Pins CS VQ CS201, CS289 VQ128 CS201, CS289 VQ176 CS281, CS289 IGLOO PLUS Devices AGLP030 AGLP060 AGLP125 I/O Type Single-Ended I/O Single-Ended I/O Single-Ended I/O CS201 120 157 — CS281 — — 212 CS289 120 157 212 VQ128 101 — — VQ176 — 137 — The low power FPGA with enhanced I/O capabilities IGLOO PLUS products deliver unrivaled low power and I/O features in a feature-rich programmable device, offering up to 64 percent more I/Os than the award-winning IGLOO products and supporting independent Schmitt trigger inputs, hot-swapping and Flash*Freeze bus hold. Ranging from 30,000 to 125,000 gates, the 1.2 V to 1.5 V IGLOO PLUS devices have been optimized to meet the needs of I/O-intensive, power-conscious applications that require exceptional features. • I/O-optimizedFPGA • UltralowpowerinFlash*Freeze mode,aslowas5µW • Lowpoweractivecapability • Smallfootprintand low-cost packages • Reprogrammable flashtechnology • 1.2Vto1.5Vsingle voltage operation • EnhancedI/Ofeatures • CCCsandPLLs • EmbeddedSRAMNVM • AES-protectedISP Notes: 1. AGLP060 in CS201 does not support the PLL. 2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125. Note: * When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended user I/Os available is reduced by one. |
类似零件编号 - U1AFS6003 |
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类似说明 - U1AFS6003 |
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