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74AHC574D118 数据表(PDF) 10 Page - NXP Semiconductors |
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74AHC574D118 数据表(HTML) 10 Page - NXP Semiconductors |
10 / 18 page 74AHC_AHCT574_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 24 January 2008 10 of 18 NXP Semiconductors 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] CPD is used to determine the dynamic power dissipation PD (µW). PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V. 10.1 Waveforms th hold time Dn to CP; see Figure 8 VCC = 4.5 V to 5.5 V; CL =50pF 1.5 - - 1.5 - 1.5 - ns CPD power dissipation capacitance per buffer; CL =50pF;f=1 MHz; VI = GND to VCC [3] -12 - - - - - pF Table 7. Dynamic characteristics …continued GND = 0 V. For test circuit see Figure 10. Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Propagation delay input (CP) to output (Qn), clock input (CP) pulse width and the maximum frequency (CP) mna802 CP input Qn output tPHL tPLH tW 1/fmax VM VOH VI GND VOL VM |
类似零件编号 - 74AHC574D118 |
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类似说明 - 74AHC574D118 |
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