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SLA7042M 数据表(PDF) 4 Page - Allegro MicroSystems |
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SLA7042M 数据表(HTML) 4 Page - Allegro MicroSystems |
4 / 8 page SLA7042M AND SLA7044M MICROSTEPPING, UNIPOLAR PWM, HIGH-CURRENT MOTOR CONTROLLER/DRIVERS 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 ™ CLOCK DATA STROBE A B D F E C D A B C Dwg. WK-002 SERIAL PORT TIMING CONDITIONS (T A = +25°C, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Clock Falling Edge (Data Set-Up Time) ........... 150 ns B. Minimum Data Active Time After Clock Falling Edge (Data Hold Time) .................. 150 ns C. Minimum Data Pulse Width ...................................................................................... 350 ns D. Minimum Clock Pulse Width .................................................................................... 350 ns E. Minimum Time Between Clock and Strobe Falling Edges ....................................... 650 ns F. Minimum Strobe Pulse Width ................................................................................... 500 ns APPLICATIONS INFORMATION The SLA7042M and SLA7044M modules integrate two CMOS controller ICs and four NMOS FETs. Each half of the device operates independently, although the CLOCK inputs may be connected together and the STROBE inputs may be connected together. Pulling V REF/EN low (<2.5 V) allows the 4- bit shift registers to be serially loaded with motor phase and output currrent ratioing data. The first bit selects the motor phase (logic high = Output A or B, logic low = Output A or B); the next three bits determine the motor current ratio (eight steps, 0% to 100%). The internal D/A converter, in conjunction with a current-sensing resistor and input reference voltage, completes the microstepping current control. Pulling V REF/EN high (within 1 V of VDD) resets the shift register and latches to turn the MOS drivers OFF and inhibits the serial DATA input. |
类似零件编号 - SLA7042M |
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类似说明 - SLA7042M |
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