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AD8116JST 数据表(PDF) 4 Page - Analog Devices |
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AD8116JST 数据表(HTML) 4 Page - Analog Devices |
4 / 29 page AD8116 –3– REV. B TIMING CHARACTERISTICS Limit Parameter Symbol Min Typ Max Unit Data Setup Time t1 20 ns CLK Pulsewidth t2 100 ns Data Hold Time t3 20 ns CLK Pulse Separation t4 100 ns CLK to UPDATE Delay t5 0ns UPDATE Pulsewidth t6 50 ns CLK to DATA OUT Valid t7 200 ns Propagation Delay, UPDATE to Switch On or Off – 50 ns Data Load Time, CLK = 5 MHz – 16 µs CLK, UPDATE Rise and Fall Times – 100 ns RESET Time – 200 ns LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE 1 0 1 0 DATA IN CLK 1 = LATCHED UPDATE 0 = TRANSPARENT DATA OUT OUT15 (D4) OUT15 (D3) OUT00 (D0) TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL t1 t3 t7 t2 t4 t6 t5 CLOCK DATA IN UPDATE 12 34 5 6 7 8 9 10 15 20 25 75 79 T = 0 INCREASING TIME 0 Figure 2. Timing Diagram and Programming Example Table I. Logic Levels VIH VIL VOH VOL IIH IIL IOH IOL CLK, DATA IN, CLK, DATA IN, DATA OUT DATA OUT CLK, DATA IN, CLK, DATA IN, DATA OUT DATA OUT CE, UPDATE CE, UPDATE CE, UPDATE CE, UPDATE 2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min |
类似零件编号 - AD8116JST |
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