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AD5293BRUZ-20-RL7 数据表(PDF) 7 Page - Analog Devices |
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AD5293BRUZ-20-RL7 数据表(HTML) 7 Page - Analog Devices |
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7 / 24 page  AD5293 Rev. D | Page 7 of 24 INTERFACE TIMING SPECIFICATIONS VDD = VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, and −40°C < TA < +105°C. All specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter Limit1 Unit Test Conditions/Comments t12 20 ns min SCLK cycle time t2 10 ns min SCLK high time t3 10 ns min SCLK low time t4 10 ns min SYNC to SCLK falling edge setup time t5 5 ns min Data setup time t6 5 ns min Data hold time t7 1 ns min SCLK falling edge to SYNC rising edge t8 4003 ns min Minimum SYNC high time t9 14 ns min SYNC rising edge to next SCLK fall ignored t104 1 ns min RDY rise to SYNC falling edge t114 40 ns max SYNC rise to RDY fall time t124 2.4 μs max RDY low time, RDAC register write command execute time (resistor performance mode) t124 410 ns max RDY low time, RDAC register write command execute time (normal mode) t124 1.5 ms max Software\hardware reset t134 450 ns max RDY low time, RDAC register read command execute time t144 450 ns max SCLK rising edge to SDO valid tRESET 20 ns min Minimum RESET pulse width (asynchronous) tPOWER-UP5 2 ms max Power-on time to half scale 1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency = 50 MHz. 3 Refer to t12 and t13 for RDAC register commands operations. 4 RPULL_UP = 2.2 kΩ to VLOGIC with a capacitance load of 168 pF. 5 Typical power supply voltage slew-rate of 2 V/ms. DATA BITS DB9 (MSB) DB0 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 CONTROL BITS C0 C1 C2 D9 D8 C3 0 0 Figure 2. Shift Register Contents |
类似零件编号 - AD5293BRUZ-20-RL7 |
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类似说明 - AD5293BRUZ-20-RL7 |
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