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TMP320F28376DPTPS 数据表(PDF) 11 Page - Texas Instruments

部件名 TMP320F28376DPTPS
功能描述  TMS320F2837XD Dual-Core Delfino Microcontrollers
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TMP320F28376DPTPS 数据表(HTML) 11 Page - Texas Instruments

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TMS320F28377D, TMS320F28376D
www.ti.com
SPRS880 – DECEMBER 2013
2.4
Bus Architecture – Peripheral Connectivity
Table 2-6 shows a broad view of the peripheral and configuration register accessibility from each bus
master. Peripherals can be individually assigned to the CPU1 or CPU2 subsystem (for example, ePWM
can be assigned to CPU1 and eQEP assigned to CPU2). Peripherals within peripheral frames 1 or 2 will
all be mapped to the respective secondary master as a group (if SPI is assigned to CPUx.DMA, then
McBSP is also assigned to CPUx.DMA).
Table 2-6. Bus Master Peripheral Access
PERIPHERALS
CPU1.DMA
CPU1.CLA1
CPU1
CPU2
CPU2.CLA1
CPU2.DMA
(BY BUS ACCESS TYPE)
Peripherals that can be assigned to CPU1 or CPU2 and have common selectable Secondary Masters
Peripheral Frame 1:
ePWM/HRPWM
Sigma-Delta Filter Module (SDFM)
Demodulator
Y
Y
Y
Y
Y
Y
eCAP(1)
eQEP(1)
CMPSS(1)
DAC(1)
Peripheral Frame 2:
SPI
Y
Y
Y
Y
Y
Y
McBSP
uPP Configuration(1)
Peripherals that can be assigned to CPU1 or CPU2 subsystems
SCI
Y
Y
I2C
Y
Y
CAN
Y
Y
ADC Configuration
Y
Y
Y
Y
EMIF1
Y
Y
Y
Y
Peripherals and Device Configuration Registers only on CPU1 subsystem
EMIF2
Y
Y
USB and USB RAM
Y
Y
Device Capability, Peripheral Reset, Peripheral
Y
CPU Select
GPIO Pin Mapping and Configuration
Y
Analog System Control
Y
uPP Message RAMs
Y
Y
Reset Configuration
Y
Accessible by only one CPU at a time with Semaphore
Clock and PLL Configuration
Y
Y
Peripherals and Registers with Unique Copies of Registers for each CPU and CLA Master(2)
System Configuration
Y
Y
(WD, NMIWD, LPM, Peripheral Clock Gating)
Flash Configuration(3)
Y
Y
CPU Timers
Y
Y
DMA and CLA Trigger Source Select
Y
Y
GPIO Data(4)
Y
Y
Y
Y
ADC Results
Y
Y
Y
Y
Y
Y
(1)
These modules are on a Peripheral Frame with DMA access; however, they do not support DMA transfers.
(2)
Each CPUx and CPUx.CLA1 can only access its own copy of these registers.
(3)
At any given time, only one CPU can perform program or erase operations on the Flash.
(4)
The GPIO Data Registers are unique for each CPUx and CPUx.CLAx. When the GPIO Pin Mapping Register is configured to assign a
GPIO to a particular master, the respective GPIO Data Register will control the GPIO. See the "General-Purpose Input/Output (GPIO)"
chapter of the TMS320F2837xD Technical Reference Manual (literature number SPRUHM8) for more details.
Copyright © 2013, Texas Instruments Incorporated
Device Overview
11
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