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DM383AAAR11 数据表(PDF) 2 Page - Texas Instruments |
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DM383AAAR11 数据表(HTML) 2 Page - Texas Instruments |
2 / 267 page DM383 SPRS870B – APRIL 2013 – REVISED DECEMBER 2013 www.ti.com • General-Purpose Memory Controller (GPMC) • Dual Controller Area Network (DCAN) Module – 8- or 16-Bit Multiplexed Address and Data – CAN Version 2 Part A, B Bus • Four Inter-Integrated Circuit (I2C Bus™) Ports – 512MB of Total Address Space Divided • Two Multichannel Audio Serial Ports (McASP) Among up to 8 Chip Selects – Six Serializer Transmit and Receive Ports – Glueless Interface to NOR Flash, NAND – Two Serializer Transmit and Receive Ports Flash (BCH/Hamming Error Code Detection), – DIT-Capable For S/PDIF (All Ports) SRAM and Pseudo-SRAM • Serial ATA (SATA) 3.0 Gbps Controller with – Error Locator Module (ELM) Outside of Integrated PHY GPMC to Provide up to 16-Bit or 512-Byte – Direct Interface to 1 Hard Disk Drive Hardware ECC for NAND – Hardware-Assisted Native Command – Flexible Asynchronous Protocol Control for Queuing (NCQ) from up to 32 Entries Interface to FPGA, CPLD, ASICs, and More – Supports Port Multiplier and Command- • Enhanced Direct Memory Access (EDMA) Based Switching Controller • Real-Time Clock (RTC) – Four Transfer Controllers – One-Time or Periodic Interrupt Generation – 64 Independent DMA Channels • Up to 125 General-Purpose I/O (GPIO) Pins – 8 QDMA Channels • One Spin Lock Module with up to 128 Hardware • Dual USB 2.0 Ports with Integrated PHYs Semaphores – USB2.0 High- and Full-Speed Clients • One Mailbox Module with 12 Mailboxes – USB2.0 High-, Full-, and Low-Speed Hosts • On-Chip ARM ROM Bootloader (RBL) – Supports End Points 0-15 • Power, Reset, and Clock Management • Eight 32-Bit General-Purpose Timers – SmartReflex™ Technology (Level 2b) (Timer1–8) – Multiple Independent Core Power Domains • One System Watchdog Timer (WDT0) – Multiple Independent Core Voltage Domains • Three Configurable UART/IrDA/CIR Modules – Support for Multiple Operating Points per – UART0 with Modem Control Signals Voltage Domain – Supports up to 3.6864 Mbps – Clock Enable and Disable Control for – SIR, MIR, FIR (4.0 MBAUD), and CIR Subsystems and Peripherals • Four Serial Peripheral Interfaces (SPIs) (up to • 32KB of Embedded Trace Buffer™ (ETB™) and 48 MHz) 5-pin Trace Interface for Debug – Each with Four Chip Selects • IEEE 1149.1 (JTAG) Compatible • Three MMC/SD/SDIO Serial Interfaces (up to • 609-Pin Pb-Free BGA Package (AAR Suffix), 48 MHz) 0.8-mm Effective Pitch with Via Channel – Supporting up to 1-, 4-, or 8-Bit Modes Technology to Reduce PCB Cost (0.5-mm Ball Spacing) • 45-nm CMOS Technology • 1.8- and 3.3-V Dual Voltage Buffers for General I/O 2 High-Performance System-on-Chip (SoC) Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DM383 |
类似零件编号 - DM383AAAR11 |
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类似说明 - DM383AAAR11 |
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