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AD7173-8BCPZ-RL 数据表(PDF) 6 Page - Analog Devices |
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AD7173-8BCPZ-RL 数据表(HTML) 6 Page - Analog Devices |
6 / 64 page AD7173-8 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit POWER DISSIPATION Full Operating Mode Unbuffered, external clock and reference; AVDD1 = 3.3 V, AVDD2 = 2 V, IOVDD = 2 V 3 mW Unbuffered, external clock and reference; all supplies = 5 V 7.35 mW Unbuffered, external clock and reference; all supplies = 5.5 V 9.96 mW Fully buffered, internal clock and reference (note that REFOUT has no load); AVDD1 = 3.3 V, AVDD2 = 2 V, IOVDD = 2 V 10.4 mW Fully buffered, internal clock and reference (note that REFOUT has no load); all supplies = 5 V 20.4 mW Fully buffered, internal clock and reference (note that REFOUT has no load); all supplies = 5.5 V 28 mW Standby Mode Reference off, all supplies = 5 V 125 µW Reference on, all supplies = 5 V 2 mW Power-Down Mode Full power-down, all supplies = 5 V 10 µW Full power-down, all supplies = 5.5 V 55 µW 1 Specification is not production tested but is supported by characterization data at the initial product release. 2 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate. 3 This specification is noncumulative and includes MSL preconditioning effects. 4 This specification includes MSL preconditioning effects. Rev. 0 | Page 6 of 64 |
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