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ADRF6620 数据表(PDF) 8 Page - Analog Devices |
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ADRF6620 数据表(HTML) 8 Page - Analog Devices |
8 / 52 page ADRF6620 Data Sheet Rev. 0 | Page 8 of 52 DIGITAL LOGIC SPECIFICATIONS Table 6. Parameter Symbol Test Conditions/Comments Min Typ Max Unit SERIAL PORT INTERFACE TIMING Input Voltage High VIH 1.4 V Input Voltage Low VIL 0.70 V Output Voltage High VOH IOH = −100 µA 2.3 V Output Voltage Low VOL IOL = +100 µA 0.2 V Serial Clock Period tSCLK 38 ns Setup Time Between Data and Rising Edge of SCLK tDS 8 ns Hold Time Between Data and Rising Edge of SCLK tDH 8 ns Setup Time Between Falling Edge of CS and SCLK tS 10 ns Hold Time Between Rising Edge of CS and SCLK tH 10 ns Minimum Period SCLK Can Be in Logic High State tHIGH 10 ns Minimum Period SCLK Can Be in Logic Low State tLOW 10 ns Maximum Time Delay Between Falling Edge of SCLK and Output Data Valid for a Read Operation tACCESS 231 ns Maximum Time Delay Between CS Deactivation and SDIO Bus Return to High Impedance tZ 5 ns Timing Diagram tS tDS tDH tHIGH tLOW tSCLK tH DON'T CARE DON'T CARE A5 A4 A3 A2 A1 A0 D15 D14 D13 D3 D2 D1 D0 DON'T CARE DON'T CARE SCLK SDIO R/W tZ tACCESS A6 CS Figure 2. Serial Port Interface Timing |
类似零件编号 - ADRF6620 |
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类似说明 - ADRF6620 |
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