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CAT28C256 数据表(PDF) 6 Page - ON Semiconductor |
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CAT28C256 数据表(HTML) 6 Page - ON Semiconductor |
6 / 14 page CAT28C256 http://onsemi.com 6 DEVICE OPERATION Read Data stored in the CAT28C256 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2−line control architecture can be used to eliminate bus contention in a system environment. Byte Write A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms. Figure 4. Read Cycle ADDRESS DATA OUT DATA VALID DATA VALID HIGH−Z tOHZ tHZ tAA tOH tOE tOLZ tCE tLZ tRC VIH CE OE WE Figure 5. Byte Write Cycle [WE Controlled] ADDRESS DATA OUT DATA IN DATA VALID HIGH−Z WE OE CE tAH tAS tCS tCH tWP tOES tOEH tBLC tDS tDH tWC |
类似零件编号 - CAT28C256 |
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类似说明 - CAT28C256 |
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