1B1

1A

OE

1B2

SW

SW

2B1

2A

2B2

SW

SW

3B1

3A

3B2

SW

SW

4B1

4A

4B2

SW

SW

S

4

7

9

12

1

15

2

3

5

6

11

10

14

13

SN74CBTLV3257

SCDS040J – DECEMBER 1997 – REVISED JANUARY 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Table 1. FUNCTION TABLE

INPUTS

FUNCTION

/OE

S

L

L

A port = B1 port

L

H

A port = B2 port

H

X

Disconnect

LOGIC DIAGRAM (POSITIVE LOGIC)

2

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