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AD50651 数据表(PDF) 5 Page - Analog Devices

部件名 AD50651
功能描述  Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD50651 数据表(HTML) 5 Page - Analog Devices

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AD5066
Rev. A | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2, VDD = 2.7 V to
5.5 V, all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.
Table 4.
Parameter1
Symbol
Min
Typ
Max
Unit
SCLK Cycle Time
t
1
20
ns
SCLK High Time
t
2
10
ns
SCLK Low Time
t
3
10
ns
SYNC to SCLK Falling Edge Set-Up Time
t
4
17
ns
Data Set-Up Time
t
5
5
ns
Data Hold Time
t
6
5
ns
SCLK Falling Edge to SYNC Rising Edge
t
7
5
30
ns
Minimum SYNC High Time
t
8
Single Channel Update
3
µs
All Channel Update
8
µs
SYNC Rising Edge to SCLK Fall Ignore
t
9
17
ns
LDAC Pulse Width Low
t
10
20
ns
SCLK Falling Edge to LDAC Rising Edge
t
11
20
ns
CLR Pulse Width Low
t
12
10
ns
SCLK Falling Edge to LDAC Falling Edge
t
13
10
ns
CLR Pulse Activation Time
t
14
10.6
µs
1 Maximum SCLK frequency is 50 MHz. Guaranteed by design and characterization; not production tested.
t4
t3
SCLK
SYNC
DIN
t1
t2
t5
t6
t7
t8
DB31
t9
t10
t11
LDAC 1
LDAC 2
t13
1ASYNCHRO NO US LDAC UPDATE M O DE.
2SYNCHRO NO US LDAC UPDATE M O DE.
CLR
t12
t14
VOUT
DB0
Figure 2. Serial Write Operation


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