数据搜索系统,热门电子元器件搜索 |
|
AD768AR 数据表(PDF) 10 Page - Analog Devices |
|
AD768AR 数据表(HTML) 10 Page - Analog Devices |
10 / 20 page REV. B –10– AD768 APPLYING THE AD768 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configura- tions for the AD768. While most figures take the output at IOUTA, IOUTB can be interchanged in all cases. Unless other- wise noted, it is assumed that IREFIN and full-scale currents are set to nominal values. For application that require the specified dc accuracies, proper resistor selection is required. In addition to absolute resistor tol- erances, resistor self-heating can result in unexpected errors. For optimal INL, the buffered voltage output is recommended as shown in Figure 23. In this configuration, self-heating of RFB may cause a change in gain, producing a bow in the INL curve. This effect can be minimized by selection of a low temperature coefficient resistor. UNBUFFERED VOLTAGE OUTPUT CONFIGURATIONS Figure 21 shows the AD768 configured to provide a unipolar output range of approximately 0 V to –1 V. The nominal full- scale current of 20 mA flows through the parallel combination of the 50 Ω R L resistor and the 1 kΩ DAC output resistance (from the R-2R ladder), for a combined 47.6 Ω. This produces an ideal full-scale voltage of –0.952 V with respect to LADCOM. In addition, the 1 k Ω DAC output resistance has a tolerance of ±20% which may vary the full-scale gain by ±1%. This linear variation results in a gain error which can be easily compensated for by adjusting IREFIN. 1 27 28 VA VB AD768 RL 49.9 Ω RL 49.9 Ω IOUTA LADCOM IOUTB Figure 21. 0 V to –1 V Unbuffered Voltage Output In this configuration, it is important to note the restrictions from the output compliance limits. The maximum negative voltage compliance is –1.2 V, prohibiting use of a 100 Ω load to produce a 0 V to –2 V output swing. One additional consideration for operation in this mode is integral nonlinearity. As the voltage at the output node changes, the finite output impedance of the DAC current steering switches gives rise to small changes in the output current that vary with output voltage, producing a bow (up to 8 LSBs) in the INL. For optimal INL performance, the buffered voltage output mode is recommended. The INL is also slightly dependent on the termination of the unused output (IOUTB) as described in the ANALOG OUT- PUT section. To eliminate this effect, IOUTB should be termi- nated with the same impedance as IOUTA, so both outputs see the same resistive divider to ground. This will keep the current in LADCOM constant, minimizing any code-dependent IR drops within the DAC ladder that may give rise to additional nonlinearities. AC-Coupled Output Configuring the output as shown in Figure 22 provides a bipolar output signal from the AD768 without requiring the use of a summing amplifier. The ac load impedance presented to the DAC output is the parallel combination of the AD768’s output impedance, RL, and bias resistor RB. The nominal output swing with the values given in Figure 22 is ±0.5 V assuming R B >> RL. The gain of the circuit will be a function of the tolerances of the impedances RLAD, RB, and RL. Choosing the value of RB and C will depend primarily on the desired –3 dB high pass cutoff frequency and the bias current, IB, of the subsequent stage connected to RB. The –3 dB fre- quency can be approximated by the equation, f–3 dB = 1/[2 × π × (R B + RL RLAD) × C]. The dc offset of the output is a function of the bias current of the subsequent stage and the value of RB. For example, if C = 390 pF, RB = 20 kΩ, and IB = 1.0 µA, the –3 dB frequency is approximately 20.4 kHz and the dc offset would be 20 mV. 1 27 28 RB AD768 RL 49.9 Ω IOUTA LADCOM IOUTB RL 49.9 Ω IB C Figure 22. 0.5 V to –0.5 V Unbuffered AC-Coupled Output BUFFERED VOLTAGE OUTPUT CONFIGURATIONS Unipolar Configuration For positive output voltages, or voltage ranges greater than allowed by output compliance limits, some type of external buffer is needed. A wide variety of amplifiers may be selected based on considerations such as speed, accuracy and cost. The AD9631 is an excellent choice when dynamic performance is important, offering low distortion up to 10 MHz. Figure 23 shows the implementation of 0 V to +2 V full-scale unipolar buffered voltage output. The amplifier establishes a summing node at ground for the DAC output. The buffered output volt- age results from the DAC output current flowing through the amplifier’s feedback resistor, RFB. In this case, the 20 mA full- scale current across RFB (100 Ω) produces an output voltage range of 0 V through +2 V. The same configuration using a pre- cision amplifier such as the AD845 is recommended for optimal dc linearity. 1 27 28 AD768 RFB 100 Ω IOUTA LADCOM IOUTB A1 Figure 23. Unipolar 0 V to +2 V Buffered Voltage Output Buffered Output Using a Current Divider The configuration shown in Figure 23 may not be possible in cases where the amplifier cannot supply the requisite 20 mA feedback current. As an alternative, Figure 24 shows amplifier A1 in conjunction with a resistive current divider. The values of RFF and RL are chosen to limit the current, I3, which must be supplied by A1. Current, I2, is shunted to ground through resis- tor, RL. The parallel combination of RFF and RL should not ex- ceed 60 Ω to avoid exceeding the specified compliance voltage. |
类似零件编号 - AD768AR |
|
类似说明 - AD768AR |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |