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LM2653MTC-ADJ 数据表(PDF) 11 Page - Texas Instruments |
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LM2653MTC-ADJ 数据表(HTML) 11 Page - Texas Instruments |
11 / 20 page LM2653 www.ti.com SNVS050E – NOVEMBER 1999 – REVISED APRIL 2013 LDELAY CAPACITOR As mentioned in the Operation section, the LDELAY capacitor sets the time delay between the output voltage goes below 80% of its nominal value and the undervoltage latch protection is enabled. Charging the CDELAY by a 5 μA current source up to 2V sets the delay time. Therefore, TDELAY = CDELAY * 2V/5 μA. The undervoltage protection is disabled by tying the LDELAY pin to the ground. R1 and R2 (PROGRAMMING OUTPUT VOLTAGE) Use the following formula to select the appropriate resistor values: VOUT = VREF(1 + R1/R2) where • VREF = 1.238V (6) Select resistors between 10k Ω and 100kΩ. (1% or higher accuracy metal film resistors for R1 and R2.) COMPENSATION COMPONENTS In the control to output transfer function, the first pole Fp1 can be estimated as 1/(2πROUTCOUT); The ESR zero Fz1 of the output capacitor is 1/(2πESRCOUT); Also, there is a high frequency pole Fp2 in the range of 45kHz to 150kHz: Fp2 = Fs/(πn(1−D)) where • D = VOUT/VIN • n = 1+0.348L/(VIN−VOUT) (L is in µHs and VIN and VOUT in volts) (7) The total loop gain G is approximately 500/IOUT where IOUT is in amperes. A Gm amplifier is used inside the LM2653. The output resistor Ro of the Gm amplifier is about 80kΩ. Cc1 and RC together with Ro give a lag compensation to roll off the gain: Fpc1 = 1/(2πCc1(Ro+Rc)), Fzc1 = 1/2πCc1Rc. (8) In some applications, the ESR zero Fz1 cannot be cancelled by Fp2. Then, Cc2 is needed to introduce Fpc2 to cancel the ESR zero, Fp2 = 1/(2πCc2Ro‖Rc). The rule of thumb is to have more than 45° phase margin at the crossover frequency (G=1). If COUT is higher than 68µF, Cc1 = 2.2nF, and Rc = 15KΩ are good choices for most applications. If the ESR zero is too low to be cancelled by Fp2, add Cc2. If the transient response to a step load is important, choose RC to be higher than 10kΩ. EXTERNAL SCHOTTKY DIODE A Schottky diode D1 is recommended to prevent the intrinsic body diode of the low-side MOSFET from conducting during the deadtime in PWM operation and hysteretic mode when both MOSFETs are off. If the body diode turns on, there is extra power dissipation in the body diode because of the reverse-recovery current and higher forward voltage; the high-side MOSFET also has more switching loss since the negative diode reverse- recovery current appears as the high-side MOSFET turn-on current in addition to the load current. These losses degrade the efficiency by 1-2%. The improved efficiency and noise immunity with the Schottky diode become more obvious with increasing input voltage and load current. The breakdown voltage rating of D1 is preferred to be 25% higher than the maximum input voltage. Since D1 is only on for a short period of time, the average current rating for D1 only requires being higher than 30% of the maximum output current. It is important to place D1 very close to the drain and source of the low-side MOSFET, extra parasitic inductance in the parallel loop will slow the turn-on of D1 and direct the current through the body diode of the low-side MOSFET. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM2653 |
类似零件编号 - LM2653MTC-ADJ |
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类似说明 - LM2653MTC-ADJ |
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