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74LVC2G17GM 数据表(PDF) 3 Page - NXP Semiconductors |
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74LVC2G17GM 数据表(HTML) 3 Page - NXP Semiconductors |
3 / 19 page 74LVC2G17 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 — 2 May 2013 3 of 19 NXP Semiconductors 74LVC2G17 Dual non-inverting Schmitt trigger with 5 V tolerant input 7. Pinning information 7.1 Pinning 7.2 Pin description 8. Functional description [1] H = HIGH voltage level; L = LOW voltage level. Fig 3. Logic diagram mnb068 1A 1Y 2A 2Y Fig 4. Pin configuration SOT363 and SOT457 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 74LVC2G17 1A 1Y GND 2A 2Y 001aaf078 1 2 3 6 VCC 5 4 74LVC2G17 GND 001aaf079 1A 2A VCC 1Y 2Y Transparent top view 2 3 1 5 4 6 74LVC2G17 GND 001aaf080 1A 2A VCC 1Y 2Y Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground (0 V) 2A 3 data input 2Y 4 data output VCC 5 supply voltage 1Y 6 data output Table 4. Function table[1] Input Output nA nY LL HH |
类似零件编号 - 74LVC2G17GM |
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类似说明 - 74LVC2G17GM |
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