CDCVF2310PWRG4 datasheet(4/16 Pages) TI

部件名	CDCVF2310PWRG4

功能描述	2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER

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制造商	TI [Texas Instruments]

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DETAILED DESCRIPTION

Output Enable Glitch Suppression Circuit

CLK

Gn

Yn

tsu(en)

th(en)

CLK

Gn

Yn

tsu(dis)

th(dis)

a) Enable Mode

b) Disable Mode

CDCVF2310

SCAS666C – JUNE 2001 – REVISED JANUARY 2008

The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the

clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative

edge triggered by the input clock) (see Figure 1).

The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for

predictable operation.

Figure 1. Enable and Disable Mode Relative to CLK

↓

4

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