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DM3730CUSD100 数据表(PDF) 5 Page - Texas Instruments |
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DM3730CUSD100 数据表(HTML) 5 Page - Texas Instruments |
5 / 280 page 64 64 Async 64 64 L2$ 256K MPU Subsystem POWERVR SGX Graphics Accelerator TM 32 32 32 Channel System DMA 32 32 Parallel TV Amp LCD Panel CVBS or S-Video Dual Output 3-Layer Display Processor (1xGraphics, 2xVideo) Temporal Dithering SDTV QCIF Support ® 32 Camera ISP Image Capture Hardware Image Pipeline Camera (Parallel) 64 HS USB Host HS USB OTG 32 L3 Interconnect Network-Hierarchial, Performance, and Power Driven 64KB On-Chip RAM 32 32KB On-Chip ROM 32 SMS: SDRAM Memory Scheduler/ Rotation 64 SDRC: SDRAM Memory Controller L4 Interconnect 32 System Controls PRCM 2xSmartReflex TM Control Module External Peripherals Interfaces Peripherals: 4xUART, 3xHigh-Speed I2C, 5xMcBSP (2x with Sidetone/Audio Buffer) 4xMcSPI, 6xGPIO 3xHigh-Speed MMC/SDIO HDQ/1 Wire, 6xMailboxes 12xGPTimers, 2xWDT, 32K Sync Timer GPMC: General Purpose Memory Controller NAND/ NOR Flash, SRAM 32 Emulation Debug: SDTI, ETM, JTAG External and Stacked Memories 32 IVA 2.2 Subsystem TMS320DM64x+ DSP Imaging Video and Audio Processor 32K/32K L1$ 48K L1D RAM 64K L2$ 32K L2 RAM 16K L2 ROM Video Hardware 64 32 Async 64 32 ARM Cortex™- A8 ® Core TrustZone 32K/32K L1$ DM3730, DM3725 www.ti.com SPRS685D – AUGUST 2010 – REVISED JULY 2011 1.3 Functional Block Diagram The functional block diagram of the DM3730/25 Digital Media Processor is shown below. Figure 1-1. DM3730/25 Functional Block Diagram Copyright © 2010–2011, Texas Instruments Incorporated DM3730, DM3725 Digital Media Processors 5 Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 |
类似零件编号 - DM3730CUSD100 |
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类似说明 - DM3730CUSD100 |
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