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AD394TD883B 数据表(PDF) 9 Page - Analog Devices |
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AD394TD883B 数据表(HTML) 9 Page - Analog Devices |
9 / 12 page AD394 Rev. A | Page 9 of 12 Figure 9. Use of Subtracter Amplifier to Preserve Accuracy OPERATION FROM ±12 V SUPPLIES The AD394 may be used with ±12 V ±5% power supplies if certain conditions are met. The most important limitation is the output swing available from the output op amps. These ampli- fiers are capable of swinging only up to 3 V from either supply. Thus, the normal ±10 V output range cannot be used. Changing the output scale is accomplished by changing the reference voltage. With a supply of ±11.4 V (5% less than ±12 V), the output range is restricted to a maximum ±8.4 V swing. It may be useful to scale the output at ±8.192 V (yielding a scale factor of 4 mV per LSB). Figure 10 shows a suggested circuit to set up a ±8.192 V output range. To help prevent poor gain drift due to a possible mis- match between RIN and RTHEVENIN of the divider network, it is recommended to buffer RIN, the potentiometer wiper voltage, with an OP-07. Figure 10. Connections for ±8.192 V Full Scale (Recommended for ±12 V Power Supplies) POWER SUPPLY DECOUPLING The power supplies used with the AD394 should be well-filtered and regulated. Local supply decoupling consisting of a 10 µF tantalum capacitor in parallel with 0.1 µF ceramic capacitor is suggested. The decoupling capacitors should be connected between the supply pins and the AGND pin. If an output booster is used, its supplies should also be decoupled to the load ground. IMPROVING FULL-SCALE STABILITY In large systems using multiple DACs, it may be desirable for all devices to share a common reference. A precision reference can greatly improve system accuracy and temperature stability. The AD2710 is a suitable reference source for such systems. It features a guaranteed maximum temperature coefficient of ±1 ppm/°C. The combination of the AD2710LN and AD394, as shown in Figure 11, yields a multiple DAC system with maxi- mum full-scale drift of ±6 ppm/°C and excellent tracking. Figure 11. Low Drift Configuration APPLICATIONS Interfacing the AD394 to Microprocessors The AD394 control logic provides a simple interface to micro- processors. The individual latches allow for multi-DAC inter- facing to a single data bus. 16-Bit Processors The AD394 is a 12-bit resolution DAC system and is easily interfaced to 16-bit wide data buses. Several possible addressing configurations exist. In the circuit shown in Figure 12, a system write signal is used to control the decoded address lines and a 74LS139 decoder driven from the least significant address bits provides the active-low CS1 through CS4 signals. In the circuit in Figure 12, address lines A0 and A1 each select a single DAC of the four contained in the AD394. The use of a separate address line for each DAC allows several DACs to be accessed simultaneously. The address lines are gated by the simultaneous occurrence of a system WR and the appropriately decoded base address. In the addressing scheme shown in Figure 12, A0 represents the least significant word address bit. Data may reside in either the 12 MSBs (left-justified) or the 12 LSBs (right-justified). Left justification is useful when the data-word represents a binary fraction of full scale, while right-justified data usually represents an integer value between 0 and 4095. Figure 12. 16-Bit Bus Interface |
类似零件编号 - AD394TD883B |
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类似说明 - AD394TD883B |
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